VHDL Code help

Tai T. OP #3435989
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Ok so when I run Isim through xilink I get this:

Simulator is doing circuit initialization process.
at 0 ps, Instance /testbench/uut/ : Warning: NUMERIC_STD."<": metavalue 
detected, returning FALSE
ERROR: In process functionT.vhd:25
 Target Size 10 and source size 20 for array dimension 0 does not match.


Is it referring to "z <= y * 3;" ????


Code:
1
library IEEE;

2
use IEEE.std_logic_1164.all;

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use IEEE.numeric_std.all;

4


5
entity functionT is

6
    port(

7
        clk: in std_logic;

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        switches: in std_logic_vector(9 downto 0);

9
        output: out std_logic_vector(9 downto 0)

10
    );

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end functionT;

12


13
architecture ARCH of functionT is

14
--signals

15
constant A: unsigned(9 downto 0):=("0110101001"); -- A=425

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signal B: unsigned(9 downto 0);

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signal sig512: unsigned(9 downto 0):=("1000000000");

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signal T: unsigned(9 downto 0);

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signal x, y, z: unsigned(9 downto 0);

20


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begin

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    B <= unsigned(switches); --something like that

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    x <= A when A>sig512 else sig512;

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    y <= x when x<B else B;

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    z <= y * 3;

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    T <= z(7 downto 0) & "00";

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    output <= std_logic_vector(T);

28
end ARCH;
Attached files:
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Tai T. OP #3436332
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Thanks I have it working. The only problem now is how to divide the "T" 
by 4 so I get the right "output". With this code T=672 and ouput=672, 
168 is the correct output meaning I need to divide by 4.


CODE:
1
library IEEE;

2
use IEEE.std_logic_1164.all;

3
use IEEE.numeric_std.all;

4


5
entity functionT is

6
    port(

7
        clk: in std_logic;

8
        output: out std_logic_vector(19 downto 0)

9
    );

10
end functionT;

11


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architecture ARCH of functionT is

13
--signals

14
signal A: unsigned(9 downto 0):=("0110101001"); -- A=425

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signal B: unsigned(9 downto 0):=("0011100000"); -- B=224

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signal sig512: unsigned(9 downto 0):=("1000000000"); -- sig512=512

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signal T: unsigned(19 downto 0);

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signal x, y: unsigned(9 downto 0);

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signal z: unsigned(19 downto 0);

20


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begin

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    x <= A when A>sig512 else sig512; --Maximum

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    y <= x when x<B else B; --Minimum

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    z <= y * 3;

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   T <= z(17 downto 0) & "00";

26
    output <= std_logic_vector(T);

27
end ARCH;
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Lothar M. Moderator (Company: Titel) #3436375
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Tai Tai wrote:
> The only problem now is how to divide the "T" by 4
Why don't you simply try it this way:  output <= std_logic_vector(T/4);
That will work, because an unsigned division by 4 is just "truncating 
the last two bits"...


BTW: why not using integer datatypes?
1
library IEEE;

2
use IEEE.std_logic_1164.all;

3
use IEEE.numeric_std.all;

4


5
entity functionT is

6
port(

7
  clk: in std_logic;

8
  inA: in std_logic_vector(19 downto 0),

9
  inB: in std_logic_vector(19 downto 0),

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  output: out std_logic_vector(9 downto 0) -- can never be longer than A or B

11
);

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end functionT;

13


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architecture ARCH of functionT is

15
--signals

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signal A: integer := 425; -- initialazation makes no sense

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signal B: integer := 224; -- because A nd B are not in registers!

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signal T, x, y: integer;

19


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begin

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  -- convert inputs to integers

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  A <= to_integer(unsigned(inA));

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  B <= to_integer(unsigned(inB));

24


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  -- do the calculation

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  x <= A when A>512 else 512; -- Maximum

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  y <= x when x<B   else B;   -- Minimum

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  T <= (y*3)/4;               -- *0.75

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  -- convert back for output

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  output <= std_logic_vector(to_unsinged(T,10));

32
end ARCH;


For the magic conversions between vectors and integers see the picture 
there:
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std
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Tai T. OP #3437617
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Yeah thanks for all your input. This the code I have working perfectly.
Thanks :)

Code:
1
library IEEE;

2
use IEEE.std_logic_1164.all;

3
use IEEE.numeric_std.all;

4


5
entity functionT is

6
    port(

7
        clk: in std_logic;

8
        output: out std_logic_vector(19 downto 0)

9
    );

10
end functionT;

11


12
architecture ARCH of functionT is

13
--signals

14
signal A: unsigned(9 downto 0):=("0010111001"); -- A=185

15
signal B: unsigned(9 downto 0):=("0100100100"); -- B=292

16
signal sig512: unsigned(9 downto 0):=("1000000000"); -- sig512=512

17
signal x, y: unsigned(9 downto 0);

18
signal z: unsigned(19 downto 0);

19


20
begin

21
    x <= A when A>sig512 else sig512; --Maximum

22
    y <= x when x<B else B; --Minimum

23
    z <= y * 3; --Multiple by 3

24
    output <= std_logic_vector(z/4); --Divide by 4

25
end ARCH;
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