Ok so when I run Isim through xilink I get this: Simulator is doing circuit initialization process. at 0 ps, Instance /testbench/uut/ : Warning: NUMERIC_STD."<": metavalue detected, returning FALSE ERROR: In process functionT.vhd:25 Target Size 10 and source size 20 for array dimension 0 does not match. Is it referring to "z <= y * 3;" ???? Code:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity functionT is port( clk: in std_logic; switches: in std_logic_vector(9 downto 0); output: out std_logic_vector(9 downto 0) ); end functionT; architecture ARCH of functionT is --signals constant A: unsigned(9 downto 0):=("0110101001"); -- A=425 signal B: unsigned(9 downto 0); signal sig512: unsigned(9 downto 0):=("1000000000"); signal T: unsigned(9 downto 0); signal x, y, z: unsigned(9 downto 0); begin B <= unsigned(switches); --something like that x <= A when A>sig512 else sig512; y <= x when x<B else B; z <= y * 3; T <= z(7 downto 0) & "00"; output <= std_logic_vector(T); end ARCH; |

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Tai Tai wrote: > Is it referring to "z <= y * 3;" ????IFit is line 25 then yes. But I'm not going to count it. It's your task to tell us, which line the error is referring to.

That is line 25. Why would I be receiving this error in isim? ERROR: In process functionT.vhd:25 Target Size 10 and source size 20 for array dimension 0 does not match.

Y is 10 bits, 3 is at least 2 bits. So the result 1023*3=3069 is 101111111101 is 12 bits but z is only 10 bits so z is too short. The error says z should be 20 bits long, not 12. I cant say why, but just do it and use the last 8 bits.

Thanks I have it working. The only problem now is how to divide the "T" by 4 so I get the right "output". With this code T=672 and ouput=672, 168 is the correct output meaning I need to divide by 4. CODE:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity functionT is port( clk: in std_logic; output: out std_logic_vector(19 downto 0) ); end functionT; architecture ARCH of functionT is --signals signal A: unsigned(9 downto 0):=("0110101001"); -- A=425 signal B: unsigned(9 downto 0):=("0011100000"); -- B=224 signal sig512: unsigned(9 downto 0):=("1000000000"); -- sig512=512 signal T: unsigned(19 downto 0); signal x, y: unsigned(9 downto 0); signal z: unsigned(19 downto 0); begin x <= A when A>sig512 else sig512; --Maximum y <= x when x<B else B; --Minimum z <= y * 3; T <= z(17 downto 0) & "00"; output <= std_logic_vector(T); end ARCH; |

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Sorry with out the whole picture it wouldn't make sense. Attached expression I was working on I need to mutilate by 0.75 so multiply by 3 then divide by 4

Tai Tai wrote: > The only problem now is how to divide the "T" by 4 Why don't you simply try it this way: output <= std_logic_vector(T/4); That will work, because an unsigned division by 4 is just "truncating the last two bits"... BTW: why not using integer datatypes?

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity functionT is port( clk: in std_logic; inA: in std_logic_vector(19 downto 0), inB: in std_logic_vector(19 downto 0), output: out std_logic_vector(9 downto 0) -- can never be longer than A or B ); end functionT; architecture ARCH of functionT is --signals signal A: integer := 425; -- initialazation makes no sense signal B: integer := 224; -- because A nd B are not in registers! signal T, x, y: integer; begin -- convert inputs to integers A <= to_integer(unsigned(inA)); B <= to_integer(unsigned(inB)); -- do the calculation x <= A when A>512 else 512; -- Maximum y <= x when x<B else B; -- Minimum T <= (y*3)/4; -- *0.75 -- convert back for output output <= std_logic_vector(to_unsinged(T,10)); end ARCH; |

For the magic conversions between vectors and integers see the picture there: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

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Why don't you just write T<=z(9 downto 0); Because attaching "00" is a left shift with 2 digits means you multiply with 4. I also see no need for T to be 20 bits long when your right output is 168 you only need 8 bits.

Gustl Buheitel wrote: > Why don't you just write > T<=z(9 downto 0); If at all such a trick, then it should be

T <= z(11 downto 2) |

Becausethenthe last two bits are truncated (whats ok for an unsigned division by 4). But all in all I prefer the z/4 style...

Hello, he has: z <= y * 3; T <= z(17 downto 0) & "00"; so T = z*4. And the output is factor 4 too high (so he says), so he could just leave away the &"00" and gets it perfectly? I think he accidentially multiplies z by 4.

Yeah thanks for all your input. This the code I have working perfectly. Thanks :) Code:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity functionT is port( clk: in std_logic; output: out std_logic_vector(19 downto 0) ); end functionT; architecture ARCH of functionT is --signals signal A: unsigned(9 downto 0):=("0010111001"); -- A=185 signal B: unsigned(9 downto 0):=("0100100100"); -- B=292 signal sig512: unsigned(9 downto 0):=("1000000000"); -- sig512=512 signal x, y: unsigned(9 downto 0); signal z: unsigned(19 downto 0); begin x <= A when A>sig512 else sig512; --Maximum y <= x when x<B else B; --Minimum z <= y * 3; --Multiple by 3 output <= std_logic_vector(z/4); --Divide by 4 end ARCH; |

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Edited by Admin