Ok so when I run Isim through xilink I get this: Simulator is doing circuit initialization process. at 0 ps, Instance /testbench/uut/ : Warning: NUMERIC_STD."<": metavalue detected, returning FALSE ERROR: In process functionT.vhd:25 Target Size 10 and source size 20 for array dimension 0 does not match. Is it referring to "z <= y * 3;" ???? Code:
1 | library IEEE; |
2 | use IEEE.std_logic_1164.all; |
3 | use IEEE.numeric_std.all; |
4 | |
5 | entity functionT is |
6 | port( |
7 | clk: in std_logic; |
8 | switches: in std_logic_vector(9 downto 0); |
9 | output: out std_logic_vector(9 downto 0) |
10 | );
|
11 | end functionT; |
12 | |
13 | architecture ARCH of functionT is |
14 | --signals
|
15 | constant A: unsigned(9 downto 0):=("0110101001"); -- A=425 |
16 | signal B: unsigned(9 downto 0); |
17 | signal sig512: unsigned(9 downto 0):=("1000000000"); |
18 | signal T: unsigned(9 downto 0); |
19 | signal x, y, z: unsigned(9 downto 0); |
20 | |
21 | begin
|
22 | B <= unsigned(switches); --something like that |
23 | x <= A when A>sig512 else sig512; |
24 | y <= x when x<B else B; |
25 | z <= y * 3; |
26 | T <= z(7 downto 0) & "00"; |
27 | output <= std_logic_vector(T); |
28 | end ARCH; |