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Forum: FPGA, VHDL & Verilog Simple Remote Control


von sam j. (sam110)


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Hey guys. I'm new to this forum and new to VHDL. I'm trying to create a 
simple remote control with three inputs Nex, Prev and Number and two 
outputs
Channel (0-9)which has the same value as Number and Video which is 
asserted when Number is "0000". The code that I've written compiles that 
problem is that it's not giving me a right answer. Please can someone 
help me find the error in my logic?

Code (includes test bench):
1
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity remote is
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  port( nex,clock,prev: in std_logic;
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        number: in std_logic_vector(3 downto 0);
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        video: out std_logic;
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        channel: out std_logic_vector(3 downto 0));
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end entity;
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architecture arch of remote is
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  signal chan:std_logic_vector (3 downto 0):=(others=>'0');
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  signal vid:std_logic;
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  type state is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
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  signal current_state, next_state: state:=S0;
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  begin
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    process(nex,prev,number)
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      begin
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        if(nex='1' or prev='1') then
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    case current_state is
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    when S0=>
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      if(nex='1' and prev='0')
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      then  next_state<=S1;
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            vid<='0';
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            chan<="0001";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S9;
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            vid<='0';
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            chan<="1001";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S0;
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            vid<='1';
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            chan<="0000";
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    end if;
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    when S1=>
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      if(nex='1' and prev='0')
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      then  next_state<=S2;
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            vid<='0';
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            chan<="0010";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S0;
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            vid<='1';
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            chan<="0000";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S1;
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            vid<='0';
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            chan<="0001";
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    end if;
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    when S2=>
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      if(nex='1' and prev='0')
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      then  next_state<=S3;
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            vid<='0';
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            chan<="0011";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S1;
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            vid<='0';
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            chan<="0001";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S2;
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            vid<='0';
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            chan<="0010";
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    end if;
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    when S3=>
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      if(nex='1' and prev='1')
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      then  next_state<=S4;
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            vid<='0';
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            chan<="0100";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S2;
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            vid<='0';
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            chan<="0010";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S3;
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            vid<='0';
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            chan<="0011";
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    end if;
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    when S4=>
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      if(nex='1' and prev='0')
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      then  next_state<=S5;
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            vid<='0';
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            chan<="0101";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S3;
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            vid<='0';
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            chan<="0011";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S4;
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            vid<='0';
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            chan<="0100";
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    end if;
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    when S5=>
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      if(nex='1' and prev='0')
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      then  next_state<=S6;
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            vid<='0';
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            chan<="0110";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S4;
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            vid<='0';
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            chan<="0100";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S5;
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            vid<='0';
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            chan<="0101";
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    end if;
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    when S6=>
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      if(nex='1' and prev='0')
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      then  next_state<=S7;
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            vid<='0';
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            chan<="0111";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S5;
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            vid<='0';
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            chan<="0101";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S6;
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            vid<='0';
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            chan<="0110";
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    end if;
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    when S7=>
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      if(nex='1' and prev='0')
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      then  next_state<=S8;
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            vid<='0';
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            chan<="1000";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S6;
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            vid<='0';
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            chan<="0110";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S7;
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            vid<='0';
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            chan<="0111";
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    end if;
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    when S8=>
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      if(nex='1' and prev='0')
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      then  next_state<=S9;
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            vid<='0';
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            chan<="1001";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S7;
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            vid<='0';
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            chan<="0111";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S8;
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            vid<='0';
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            chan<="1000";
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    end if;
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    when S9=>
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      if(nex='1' and prev='0')
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      then  next_state<=S0;
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            vid<='1';
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            chan<="0000";
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      elsif(nex='0' and prev='1')
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      then  next_state<=S8;
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            vid<='0';
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            chan<="1000";
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      elsif(nex='1' and prev='1')
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      then  next_state<=S9;
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            vid<='0';
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            chan<="1001";
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    end if;
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end case;
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else
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  case number is
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    when "0000"=>
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      next_state<=S0;
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      vid<='1';
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      chan<="0000";
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    when "0001"=>
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      next_state<=S1;
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      vid<='0';
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      chan<="0001";
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    when "0010"=>
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      next_state<=S2;
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      vid<='0';
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      chan<="0010";
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    when "0011"=>
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      next_state<=S3;
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      vid<='0';
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      chan<="0011";
195
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    when "0100"=>
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      next_state<=S4;
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      vid<='0';
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      chan<="0100";
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    when "0101"=>
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      next_state<=S5;
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      vid<='0';
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      chan<="0101";
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    when "0110"=>
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      next_state<=S6;
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      vid<='0';
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      chan<="0110";
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    when "0111"=>
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      next_state<=S7;
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      vid<='0';
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      chan<="0111";
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    when "1000"=>
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      next_state<=S8;
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      vid<='0';
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      chan<="1000";
220
      
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    when "1001"=>
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      next_state<=S9;
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      vid<='0';
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      chan<="1001";
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    when others=>
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      next_state<=S0;
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      vid<='1';
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      chan<="0000";
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230
      
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      end case;
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end if;
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end process;
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SEQ: process(clock)
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begin
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if clock'event and clock = '1' then
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current_state <= next_state;
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video<=vid;
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channel<=chan;
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end if;
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end process SEQ;
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end arch;
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------------------------------------------------   
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test bench:
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity testbench is
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end testbench;
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architecture testbench of testbench is 
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component remote port(nex,clock,prev: in std_logic;
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        number: in std_logic_vector(3 downto 0);
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        video: out std_logic;
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        channel: out std_logic_vector(3 downto 0));
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end component;
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signal nex : std_logic := '0';
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signal prev : std_logic := '0';
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signal clock : std_logic := '0';
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signal number : std_logic_vector(3 downto 0) := "0000";
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signal video : std_logic;
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signal channel : std_logic_vector(3 downto 0);
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begin
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  UUT: remote port map (nex => nex, prev => prev, clock => clock, number => number, video => video, channel => channel);
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    process 
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      begin
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        Clock <= '0' ; wait for 20 ns;
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        Clock <= '1' ; wait for 20 ns;
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    end process;
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    process
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      begin
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        number <= "0110"; nex <= '1'; prev <= '0'; wait for 30 ns;
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        number <= "0110"; nex <= '0'; prev <= '1'; wait for 230 ns;
287
    end process;
288
end testbench;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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sam johnson wrote:
> The code that I've written compiles that problem is that it's not giving
> me a right answer.
What answer do you expect and what answer do you get?

BTW:
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    *Post long source code as attachment, not in the text*

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