1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 |
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6 | entity remote is
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7 | port( nex,clock,prev: in std_logic;
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8 | number: in std_logic_vector(3 downto 0);
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9 | video: out std_logic;
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10 | channel: out std_logic_vector(3 downto 0));
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11 | end entity;
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12 |
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13 | architecture arch of remote is
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14 | signal chan:std_logic_vector (3 downto 0):=(others=>'0');
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15 | signal vid:std_logic;
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16 | type state is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
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17 | signal current_state, next_state: state:=S0;
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18 | begin
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19 | process(nex,prev,number)
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20 | begin
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21 | if(nex='1' or prev='1') then
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22 | case current_state is
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23 | when S0=>
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24 | if(nex='1' and prev='0')
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25 | then next_state<=S1;
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26 | vid<='0';
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27 | chan<="0001";
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28 | elsif(nex='0' and prev='1')
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29 | then next_state<=S9;
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30 | vid<='0';
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31 | chan<="1001";
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32 | elsif(nex='1' and prev='1')
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33 | then next_state<=S0;
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34 | vid<='1';
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35 | chan<="0000";
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36 | end if;
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37 |
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38 | when S1=>
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39 | if(nex='1' and prev='0')
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40 | then next_state<=S2;
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41 | vid<='0';
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42 | chan<="0010";
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43 | elsif(nex='0' and prev='1')
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44 | then next_state<=S0;
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45 | vid<='1';
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46 | chan<="0000";
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47 | elsif(nex='1' and prev='1')
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48 | then next_state<=S1;
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49 | vid<='0';
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50 | chan<="0001";
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51 | end if;
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52 |
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53 | when S2=>
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54 | if(nex='1' and prev='0')
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55 | then next_state<=S3;
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56 | vid<='0';
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57 | chan<="0011";
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58 | elsif(nex='0' and prev='1')
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59 | then next_state<=S1;
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60 | vid<='0';
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61 | chan<="0001";
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62 | elsif(nex='1' and prev='1')
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63 | then next_state<=S2;
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64 | vid<='0';
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65 | chan<="0010";
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66 | end if;
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67 |
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68 | when S3=>
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69 | if(nex='1' and prev='1')
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70 | then next_state<=S4;
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71 | vid<='0';
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72 | chan<="0100";
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73 | elsif(nex='0' and prev='1')
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74 | then next_state<=S2;
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75 | vid<='0';
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76 | chan<="0010";
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77 | elsif(nex='1' and prev='1')
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78 | then next_state<=S3;
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79 | vid<='0';
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80 | chan<="0011";
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81 | end if;
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82 |
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83 | when S4=>
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84 | if(nex='1' and prev='0')
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85 | then next_state<=S5;
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86 | vid<='0';
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87 | chan<="0101";
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88 | elsif(nex='0' and prev='1')
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89 | then next_state<=S3;
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90 | vid<='0';
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91 | chan<="0011";
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92 | elsif(nex='1' and prev='1')
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93 | then next_state<=S4;
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94 | vid<='0';
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95 | chan<="0100";
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96 | end if;
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97 |
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98 | when S5=>
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99 | if(nex='1' and prev='0')
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100 | then next_state<=S6;
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101 | vid<='0';
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102 | chan<="0110";
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103 | elsif(nex='0' and prev='1')
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104 | then next_state<=S4;
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105 | vid<='0';
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106 | chan<="0100";
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107 | elsif(nex='1' and prev='1')
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108 | then next_state<=S5;
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109 | vid<='0';
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110 | chan<="0101";
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111 | end if;
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112 |
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113 | when S6=>
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114 | if(nex='1' and prev='0')
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115 | then next_state<=S7;
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116 | vid<='0';
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117 | chan<="0111";
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118 | elsif(nex='0' and prev='1')
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119 | then next_state<=S5;
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120 | vid<='0';
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121 | chan<="0101";
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122 | elsif(nex='1' and prev='1')
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123 | then next_state<=S6;
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124 | vid<='0';
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125 | chan<="0110";
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126 | end if;
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127 |
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128 | when S7=>
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129 | if(nex='1' and prev='0')
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130 | then next_state<=S8;
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131 | vid<='0';
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132 | chan<="1000";
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133 | elsif(nex='0' and prev='1')
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134 | then next_state<=S6;
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135 | vid<='0';
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136 | chan<="0110";
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137 | elsif(nex='1' and prev='1')
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138 | then next_state<=S7;
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139 | vid<='0';
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140 | chan<="0111";
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141 | end if;
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142 |
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143 | when S8=>
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144 | if(nex='1' and prev='0')
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145 | then next_state<=S9;
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146 | vid<='0';
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147 | chan<="1001";
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148 | elsif(nex='0' and prev='1')
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149 | then next_state<=S7;
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150 | vid<='0';
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151 | chan<="0111";
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152 | elsif(nex='1' and prev='1')
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153 | then next_state<=S8;
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154 | vid<='0';
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155 | chan<="1000";
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156 | end if;
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157 |
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158 | when S9=>
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159 | if(nex='1' and prev='0')
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160 | then next_state<=S0;
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161 | vid<='1';
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162 | chan<="0000";
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163 | elsif(nex='0' and prev='1')
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164 | then next_state<=S8;
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165 | vid<='0';
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166 | chan<="1000";
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167 | elsif(nex='1' and prev='1')
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168 | then next_state<=S9;
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169 | vid<='0';
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170 | chan<="1001";
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171 | end if;
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172 | end case;
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173 | else
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174 | case number is
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175 |
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176 | when "0000"=>
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177 | next_state<=S0;
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178 | vid<='1';
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179 | chan<="0000";
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180 |
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181 | when "0001"=>
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182 | next_state<=S1;
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183 | vid<='0';
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184 | chan<="0001";
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185 |
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186 | when "0010"=>
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187 | next_state<=S2;
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188 | vid<='0';
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189 | chan<="0010";
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190 |
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191 | when "0011"=>
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192 | next_state<=S3;
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193 | vid<='0';
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194 | chan<="0011";
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195 |
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196 | when "0100"=>
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197 | next_state<=S4;
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198 | vid<='0';
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199 | chan<="0100";
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200 |
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201 | when "0101"=>
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202 | next_state<=S5;
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203 | vid<='0';
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204 | chan<="0101";
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205 |
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206 | when "0110"=>
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207 | next_state<=S6;
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208 | vid<='0';
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209 | chan<="0110";
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210 |
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211 | when "0111"=>
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212 | next_state<=S7;
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213 | vid<='0';
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214 | chan<="0111";
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215 |
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216 | when "1000"=>
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217 | next_state<=S8;
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218 | vid<='0';
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219 | chan<="1000";
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220 |
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221 | when "1001"=>
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222 | next_state<=S9;
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223 | vid<='0';
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224 | chan<="1001";
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225 | when others=>
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226 | next_state<=S0;
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227 | vid<='1';
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228 | chan<="0000";
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229 |
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230 |
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231 | end case;
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232 | end if;
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233 |
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234 | end process;
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235 |
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236 | SEQ: process(clock)
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237 | begin
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238 | if clock'event and clock = '1' then
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239 | current_state <= next_state;
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240 | video<=vid;
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241 | channel<=chan;
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242 | end if;
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243 | end process SEQ;
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244 |
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245 | end arch;
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246 |
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247 | ------------------------------------------------
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248 | test bench:
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249 |
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250 | library ieee;
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251 | use ieee.std_logic_1164.all;
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252 | use ieee.std_logic_arith.all;
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253 | use ieee.std_logic_unsigned.all;
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254 |
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255 | entity testbench is
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256 | end testbench;
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257 |
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258 | architecture testbench of testbench is
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259 |
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260 | component remote port(nex,clock,prev: in std_logic;
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261 | number: in std_logic_vector(3 downto 0);
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262 | video: out std_logic;
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263 | channel: out std_logic_vector(3 downto 0));
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264 | end component;
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265 |
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266 | signal nex : std_logic := '0';
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267 | signal prev : std_logic := '0';
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268 | signal clock : std_logic := '0';
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269 | signal number : std_logic_vector(3 downto 0) := "0000";
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270 | signal video : std_logic;
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271 | signal channel : std_logic_vector(3 downto 0);
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272 |
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273 | begin
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274 |
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275 | UUT: remote port map (nex => nex, prev => prev, clock => clock, number => number, video => video, channel => channel);
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276 | process
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277 | begin
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278 | Clock <= '0' ; wait for 20 ns;
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279 | Clock <= '1' ; wait for 20 ns;
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280 | end process;
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281 |
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282 | process
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283 | begin
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284 |
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285 | number <= "0110"; nex <= '1'; prev <= '0'; wait for 30 ns;
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286 | number <= "0110"; nex <= '0'; prev <= '1'; wait for 230 ns;
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287 | end process;
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288 | end testbench;
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