von
vhdl n.
(Company: none)
(pranoy )
2013-12-03 03:21
1 --alu--
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 use ieee . std_logic_unsigned . all ;
6 entity alu_ent is
7 port (
8 x , y : in std_logic_vector ( 7 downto 0 );
9 a : in std_logic_vector ( 2 downto 0 );
10 z : out std_logic_vector ( 7 downto 0 )
11 );
12 end alu_ent ;
13 architecture alu_arch of alu_ent is
14
15 signal reg_a_data : std_logic_vector ( 7 downto 0 );
16 signal reg_b_data : std_logic_vector ( 7 downto 0 );
17 begin
18 process ( x , y , a )
19 begin
20 case a is
21 when "000" =>
22 z <= x + y ;
23 when "001" =>
24 z <= x - y ;
25 when "010" =>
26 reg_a_data <= y ;
27 reg_b_data <= y ;
28 z <= "XXXXXXXX" ;
29 when "011" =>
30 z <= x and y ;
31 when "100" =>
32 z <= x or y ;
33 when "101" =>
34 reg_b_data <= x ;
35 reg_a_data <= x ;
36 z <= "XXXXXXXX" ;
37
38 when others => z <= "XXXXXXXX" ;
39 end case ;
40 end process ;
41 end alu_arch ;
1 --register--
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 use ieee . std_logic_arith . all ;
6 use ieee . std_logic_unsigned . all ;
7
8 entity reg_new is
9 port ( control : in std_logic_vector ( 2 downto 0 );
10 data_in : in std_logic_vector ( 7 downto 0 );
11 data_out : out std_logic_vector ( 7 downto 0 )
12 );
13 end reg_new ;
14
15 architecture behav of reg_new is
16 subtype cell is std_logic_vector ( 7 downto 0 );
17 type memarray is array ( 0 downto 0 ) of cell ;
18 signal mem : memarray ;
19 begin
20 process ( control )
21 variable ctrl : std_logic_vector ( 2 downto 0 );
22 begin
23 ctrl : = control ;
24 case ctrl is
25
26 when "101" =>
27 data_out <= mem ( 0 );
28 when "110" =>
29 mem ( 0 ) <= data_in ;
30 data_out <= ( others => 'Z' );
31 when others =>
32 data_out <= ( others => 'Z' );
33 end case ;
34 end process ;
35 end behav ;
1 --datapath--
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 use ieee . std_logic_unsigned . all ;
6 entity datapath_latest is
7 port (
8 D1 , D2 : in std_logic_vector ( 7 downto 0 );
9 Dout : out std_logic_vector ( 7 downto 0 );
10 control : in std_logic_vector ( 2 downto 0 );
11 load : in std_logic_vector ( 2 downto 0 )
12 );
13 end datapath_latest ;
14 architecture behav of datapath_latest is
15 signal reg_a_data : std_logic_vector ( 7 downto 0 );
16 signal reg_b_data : std_logic_vector ( 7 downto 0 );
17
18
19 component reg_new
20
21 port ( control : in std_logic_vector ( 2 downto 0 );
22 data_in : in std_logic_vector ( 7 downto 0 );
23 data_out : out std_logic_vector ( 7 downto 0 ));
24 end component ;
25
26
27
28 component alu_ent
29 port (
30 x , y : in std_logic_vector ( 7 downto 0 );
31 a : in std_logic_vector ( 2 downto 0 );
32 z : out std_logic_vector ( 7 downto 0 )
33 );
34 end component ;
35 begin
36 register_a : reg_new
37 port map (
38 data_in => D1 ,
39 control => load ,
40 data_out => reg_a_data
41 ) ;
42
43 register_b : reg_new
44 port map (
45 data_in => D2 ,
46 control => load ,
47 data_out => reg_b_data
48 ) ;
49
50 alu : alu_ent
51 port map ( x => reg_a_data ,
52 y => reg_b_data ,
53 z => Dout ,
54 a => control
55 );
56
57 end behav ;
guys these are my components.
but i can't perform the move operation when i force the signals in
modelsim.
can any one please help me with this?
how should i modify my code so that the control signals will come
automatically?
von
Lothar M.
(Company: Titel)
(lkmiller )
(Moderator )
2013-12-03 06:14
vhdl newbie wrote: > but i can't perform the move operation when i force the signals in
> modelsim.
Why not? What problem do you encounter? What should happen? What does
happen?
> i force the signals in modelsim.
Write a testbench. Thats what VHDL is made for...
vhdl newbie wrote: 1 variable ctrl : std_logic_vector ( 2 downto 0 );
2 begin
3 ctrl : = control ;
4 case ctrl is
Why the heck do you use a (absolutely and completely unnecessary)
variable here? You could have written something like this instead: 1 begin
2 case control is
2013-12-03 06:14 :
Edited by Moderator
von
vhdl n.
(Company: none)
(pranoy )
2013-12-05 15:51
@Lothar Miller
thank you sir.
i did some changes to my programs.
but now i can't even compile it.
PLZ help me.
the programs are given below.
1 --datapath
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 --use ieee.std_logic_unsigned.all;
6
7 entity datapath_latest is
8 port (
9 D1 : in std_logic_vector ( 7 downto 0 );
10 D2 : in std_logic_vector ( 7 downto 0 );
11 Dout : out std_logic_vector ( 7 downto 0 );
12 control : in std_logic_vector ( 2 downto 0 );
13 load : in std_logic_vector ( 2 downto 0 )
14 );
15 end datapath_latest ;
16
17 architecture behav of datapath_latest is
18 signal reg_a_data_in : std_logic_vector ( 7 downto 0 );
19 signal reg_b_data_in : std_logic_vector ( 7 downto 0 );
20 signal reg_a_data_out : std_logic_vector ( 7 downto 0 );
21 signal reg_b_data_out : std_logic_vector ( 7 downto 0 );
22 signal a_move : std_logic_vector ( 7 downto 0 );
23 signal b_move : std_logic_vector ( 7 downto 0 );
24 signal d1_signal : std_logic_vector ( 7 downto 0 );
25 signal d2_signal : std_logic_vector ( 7 downto 0 );
26 signal sel_signal : std_logic ;
27
28
29 component reg_new
30
31 port ( control : in std_logic_vector ( 2 downto 0 );
32 data_in : in std_logic_vector ( 7 downto 0 );
33 data_out : out std_logic_vector ( 7 downto 0 ));
34 end component ;
35
36
37
38 component alu_ent
39 port (
40 x , y : in std_logic_vector ( 7 downto 0 );
41 a : in std_logic_vector ( 2 downto 0 );
42 reg_a_mov , reg_b_mov : out std_logic_vector ( 7 downto 0 );
43 sel : in std_logic ;
44 z : out std_logic_vector ( 7 downto 0 )
45 );
46 end component ;
47
48 component MUX
49 port (
50 d0 : in std_logic_vector ( 7 downto 0 );
51 d1 : in std_logic_vector ( 7 downto 0 );
52 s : in std_logic ;
53 y : out std_logic_vector ( 7 downto 0 )
54 );
55 end component ;
56
57 begin
58
59 mux_a : MUX
60
61 port map (
62 d0 => a_move ,
63 d1 => D1 ,
64 s => sel_signal ,
65 y => reg_a_data_in
66 );
67
68 mux_b : MUX
69
70 port map (
71 d0 => b_move ,
72 d1 => D2 ,
73 s => sel_signal ,
74 y => reg_b_data_in
75 );
76
77 register_a : reg_new
78 port map (
79 data_in => reg_a_data_in ,
80 control => load ,
81 data_out => reg_a_data_out
82 ) ;
83
84 register_b : reg_new
85 port map (
86 data_in => reg_b_data_in ,
87 control => load ,
88 data_out => reg_b_data_out
89 ) ;
90
91 alu : alu_ent
92 port map ( x => reg_a_data_out ,
93 y => reg_b_data_out ,
94 z => Dout ,
95 reg_a_mov => a_mov ,
96 reg_b_mov => b_mov ,
97 a => control ,
98 sel => sel_signal
99 );
100
101 end behav ;
1 --alu
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 use ieee . std_logic_unsigned . all ;
6 entity alu_ent is
7 port (
8 x , y : in std_logic_vector ( 7 downto 0 );
9 a : in std_logic_vector ( 2 downto 0 );
10 reg_a_mov , reg_b_mov : out std_logic_vector ( 7 downto 0 );
11 sel : in std_logic ;
12 z : out std_logic_vector ( 7 downto 0 )
13 );
14 end alu_ent ;
15 architecture alu_arch of alu_ent is
16
17
18 begin
19 process ( x , y , a )
20 begin
21
22 case a is
23 when "000" =>
24 z <= x + y ;
25 reg_a_mov <= "XXXXXXXX" ;
26 reg_b_mov <= "XXXXXXXX" ;
27 sel <= '1' ;
28 when "001" =>
29 z <= x - y ;
30 reg_a_mov <= "XXXXXXXX" ;
31 reg_b_mov <= "XXXXXXXX" ;
32 sel <= '1' ;
33 when "010" =>
34 reg_a_mov <= y ;
35 reg_b_mov <= y ;
36 z <= "XXXXXXXX" ;
37 sel <= '0' ;
38 when "011" =>
39 z <= x and y ;
40 reg_a_mov <= "XXXXXXXX" ;
41 reg_b_mov <= "XXXXXXXX" ;
42 sel <= '1' ;
43 when "100" =>
44 z <= x or y ;
45 reg_a_mov <= "XXXXXXXX" ;
46 reg_b_mov <= "XXXXXXXX" ;
47 sel <= '1' ;
48 when "101" =>
49 reg_b_mov <= x ;
50 reg_a_mov <= x ;
51 z <= "XXXXXXXX" ;
52 sel <= '0' ;
53
54 when others =>
55 z <= "XXXXXXXX" ;
56 reg_a_mov <= "XXXXXXXX" ;
57 reg_b_mov <= "XXXXXXXX" ;
58 sel <= '1' ;
59 end case ;
60 end process ;
61 end alu_arch ;
1 --register
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 use ieee . std_logic_arith . all ;
6 use ieee . std_logic_unsigned . all ;
7
8 entity reg_new is
9 port ( control : in std_logic_vector ( 2 downto 0 );
10 data_in : in std_logic_vector ( 7 downto 0 );
11 data_out : out std_logic_vector ( 7 downto 0 )
12 );
13 end reg_new ;
14
15 architecture behav of reg_new is
16 subtype cell is std_logic_vector ( 7 downto 0 );
17 type memarray is array ( 0 downto 0 ) of cell ;
18 signal mem : memarray ;
19 begin
20 process ( control )
21 begin
22
23 case control is
24
25 when "101" =>
26 data_out <= mem ( 0 );
27 when "110" =>
28 mem ( 0 ) <= data_in ;
29 data_out <= ( others => 'Z' );
30 when others =>
31 data_out <= ( others => 'Z' );
32 end case ;
33 end process ;
34 end behav ;
1 --mux
2
3 library ieee ;
4 use ieee . std_logic_1164 . all ;
5 entity MUX is
6 port ( d0 , d1 : in std_logic_vector ( 7 downto 0 );
7 s : in std_logic ;
8 y : out std_logic_vector ( 7 downto 0 )
9 );
10 end MUX ;
11
12 architecture MUX_arch of MUX is
13 begin
14 process ( d0 , d1 , s )
15 begin
16 case s is
17 when '0' =>
18 y <= d0 ;
19 when '1' =>
20 y <= d1 ;
21 when others =>
22 y <= "ZZZZZZZZ" ;
23 end case ;
24 end process ;
25 end MUX_arch ;
i get the following errors when i compile the datapath.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(53): Cannot
assign to object "d1" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(54): Cannot
assign to object "d2" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(58): VHDL
Compiler exiting
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