--alu--library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu_ent isport(
x,y:instd_logic_vector(7downto0);
a:instd_logic_vector(2downto0);
z:outstd_logic_vector(7downto0)
);
end alu_ent;
architecture alu_arch of alu_ent issignal reg_a_data : std_logic_vector(7downto0 );
signal reg_b_data : std_logic_vector(7downto0 );
beginprocess(x,y,a)
begincase a iswhen"000"=>
z<=x+y;
when"001"=>
z<=x-y;
when"010"=>
reg_a_data<=y;
reg_b_data<=y;
z<="XXXXXXXX";
when"011"=>
z<=x and y;
when"100"=>
z<=x or y;
when"101"=>
reg_b_data<=x;
reg_a_data<=x;
z<="XXXXXXXX";
whenothers=> z<="XXXXXXXX";
endcase;
endprocess;
end alu_arch;
--register--library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_new isport( control:instd_logic_vector(2downto0);
data_in:instd_logic_vector(7downto0);
data_out:outstd_logic_vector(7downto0)
);
end reg_new;
architecture behav of reg_new issubtype cell isstd_logic_vector(7downto0);
type memarray isarray(0downto0) of cell;
signal mem:memarray;
beginprocess(control)
variable ctrl:std_logic_vector(2downto0);
begin
ctrl:=control;
case ctrl iswhen"101"=>
data_out<=mem(0);
when"110"=>
mem(0)<=data_in;
data_out<=(others=>'Z');
whenothers=>
data_out<=(others=>'Z');
endcase;
endprocess;
end behav;
guys these are my components.
but i can't perform the move operation when i force the signals in
modelsim.
can any one please help me with this?
how should i modify my code so that the control signals will come
automatically?
vhdl newbie wrote:> but i can't perform the move operation when i force the signals in> modelsim.
Why not? What problem do you encounter? What should happen? What does
happen?
> i force the signals in modelsim.
Write a testbench. Thats what VHDL is made for...
vhdl newbie wrote:
variable ctrl:std_logic_vector(2downto0);
begin
ctrl:=control;
case ctrl is
Why the heck do you use a (absolutely and completely unnecessary)
variable here? You could have written something like this instead:
--alulibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu_ent isport(
x,y:instd_logic_vector(7downto0);
a:instd_logic_vector(2downto0);
reg_a_mov,reg_b_mov:outstd_logic_vector(7downto0 );
sel:instd_logic;
z:outstd_logic_vector(7downto0)
);
end alu_ent;
architecture alu_arch of alu_ent isbeginprocess(x,y,a)
begincase a iswhen"000"=>
z<=x+y;
reg_a_mov<="XXXXXXXX";
reg_b_mov<="XXXXXXXX";
sel<='1';
when"001"=>
z<=x-y;
reg_a_mov<="XXXXXXXX";
reg_b_mov<="XXXXXXXX";
sel<='1';
when"010"=>
reg_a_mov<=y;
reg_b_mov<=y;
z<="XXXXXXXX";
sel<='0';
when"011"=>
z<=x and y;
reg_a_mov<="XXXXXXXX";
reg_b_mov<="XXXXXXXX";
sel<='1';
when"100"=>
z<=x or y;
reg_a_mov<="XXXXXXXX";
reg_b_mov<="XXXXXXXX";
sel<='1';
when"101"=>
reg_b_mov<=x;
reg_a_mov<=x;
z<="XXXXXXXX";
sel<='0';
whenothers=>
z<="XXXXXXXX";
reg_a_mov<="XXXXXXXX";
reg_b_mov<="XXXXXXXX";
sel<='1';
endcase;
endprocess;
end alu_arch;
--registerlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_new isport( control:instd_logic_vector(2downto0);
data_in:instd_logic_vector(7downto0);
data_out:outstd_logic_vector(7downto0)
);
end reg_new;
architecture behav of reg_new issubtype cell isstd_logic_vector(7downto0);
type memarray isarray(0downto0) of cell;
signal mem:memarray;
beginprocess(control)
begincase control iswhen"101"=>
data_out<=mem(0);
when"110"=>
mem(0)<=data_in;
data_out<=(others=>'Z');
whenothers=>
data_out<=(others=>'Z');
endcase;
endprocess;
end behav;
--muxlibrary ieee;
use ieee.std_logic_1164.all;
entity MUX isport(d0,d1:instd_logic_vector(7downto0);
s:instd_logic;
y:outstd_logic_vector(7downto0)
);
end MUX;
architecture MUX_arch of MUX isbeginprocess(d0,d1,s)
begincase s iswhen'0'=>
y<=d0;
when'1'=>
y<=d1;
whenothers=>
y<="ZZZZZZZZ";
endcase;
endprocess;
end MUX_arch;
i get the following errors when i compile the datapath.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(53): Cannot
assign to object "d1" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(54): Cannot
assign to object "d2" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(58): VHDL
Compiler exiting