Hello. I am new in VHDL. I try to create train ticket machine using vhdl. It have 3 destination and all destination have fee. When user insert money with same of fee, ticket will out and no change but if user enter extra money than fee, ticket will out also with change.When i run the simulation all output does not appear but it appear UUU. Anybody can help me with my code,please. Thanks. God bless you.
You should watch the p_State signal, and look, why it dows not get in to the state, which sets the return.
Hello, why aren't you Reset "ticket, money_sum and retrn"? Add them to your rst or reset them in the State before. Mfg Dennis
Thanks for reply. i already look p_state and i don't know which line the error.
I already add reset ticket,money_sum and retrn but i got error after compile it.Assume that I am zero in vhdl. Thanks
Schmidt n. wrote: > Anybody can help me with my code,please. Your code is doing exactly what you described... You can have a closer look to the signals inside the entity trainticket_machine. Just dig around a littlte bit in the simulators projekt structure (the projekt window is on the left halnd side to your screenshot)... Money_sum is missing in this sensitivity list, so the simulation is wrong:
But after adding it you will find an issue with a combinational loop with all those statements:
Money_sum <= Money_sum + 1; -- also +2 and +5...
BTW: Never ever use all of the arithmetic libs:
You will have some definitions doubled and you will encounter courious problems with that... Schmidt n. wrote: > Assume that I am zero in vhdl. So, why not starting with a much simpler project like an counter or something else?
Thanks. I already add Money_sum into my simulation. BTW if i never use those library what should I used because when I enable it my code have many errors. Yes, I am not much know about VHDL. Thanks for advice.
Schmidt n. wrote: > Thanks. I already add Money_sum into my simulation. > > BTW if i never use those library what should I used because when I > disable it my code have many errors. > > Yes, I am not much know about VHDL. Thanks for advice.
Schmidt n. wrote: > BTW if i never use those library what should I used because when I > enable it my code have many errors. Start thinking, not copying. The numeric_std has all to handle conversions from vector types to integer and to deal with vectorized calculations. You just cannot add two std_logic_vector directly, but instead you must use the signed or unsigned vectors. All in all its absolutely no rocket science and its done by millions of students before. Think about it... One thing more: > Money_sum : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) Using INOUT just for laziness or for some kind of "short and compact code"? In which book did you find this? Throw it away! Never ever try to "simplify" your beginners code with such dirty tricks. Instead have a look inside books of Peter Ashenden, he is very close to the VHDL standards because he works in the VHDL standardization panel.
Alright. Thanks for your response and adviced