1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.std_logic_arith.all; |
4 | use ieee.std_logic_unsigned.all; |
5 | entity SRAM is |
6 | generic(width:integer:=4;depth:integer:=32;addr:integer:=5); |
7 | port(Clock:in std_logic; |
8 | Enable:in std_logic; |
9 | Read:in std_logic; |
10 | Write:in std_logic; |
11 | Read_Addr:in std_logic_vector(addr-1 downto 0); |
12 | Write_Addr: in std_logic_vector(addr-1 downto 0); |
13 | Data_in: in std_logic_vector(width-1 downto 0); |
14 | Data_out: out std_logic_vector(width-1 downto 0)); |
15 | end SRAM; |
16 | |
17 | architecture behav of SRAM is |
18 | type ram_type is array (0 to depth-1) of |
19 | std_logic_vector(width-1 downto 0); |
20 | signal tmp_ram:ram_type; |
21 | begin
|
22 | process(clock,read) |
23 | begin
|
24 | if(clock'event and clock='1') then |
25 | if enable='1' then |
26 | if read='1' then |
27 | data_out<=tmp_ram(conv_integer(read_addr)); |
28 | else
|
29 | data_out<=(data_out'range=>'Z'); |
30 | end if; |
31 | end if; |
32 | end if; |
33 | end process; |
34 | process(clock,write) |
35 | begin
|
36 | if(clock'event and clock='1') then |
37 | if enable='1' then |
38 | if write='1' then |
39 | tmp_ram(conv_integer(write_addr))<=data_in; |
40 | end if; |
41 | end if; |
42 | end if; |
43 | end process; |
44 | end behav; |
i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM. pls help me to find the error.
:
Edited by Moderator
vhdl newbie wrote: > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; Why do you use obsolete librarys? Link: http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector
1 | ... |
2 | However, these packages are NOT standard, and different vendors have |
3 | different and mutually incompatible versions. Also, there are naming clashes |
4 | when some of these packages are used together. So, it is recommended that |
5 | numeric_bit or numeric_std be used in preference to these non-standard packages. |
> i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM.
Beside the librarys the code looks ok. Did you restart your simulation?
How did you recognize the non-functionality?
Duke
vhdl newbie wrote: > process(clock,read) > process(clock,write) These processes are synchronous and therefore only dependent on the clock. So read and write are too much in the sensitivity lists... > depth:integer:=32; addr:integer:=5 These two values are relatives to themselves. So it would be enough to define one of them, then the other can be calculated: type ram_type is array (0 to (2**addr)-1) of ... > i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM. How did you find this out?
1.It is advisable to perform a write cycle first and then read the data ad the data will be in undefined state if you read first. 2. There is no need for 3 parameters(width, depth, addr.). Two are enough. And data_in and data_out must be (depth - 1 downto 0) if you want a 4*32 RAM. If you declare them as (width - 1 downto 0), a 4*4 RAM will be created. In your code, you can remove the width parameter. Depth and addr. are enough. --Regards
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