library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity SRAM is generic(width:integer:=4;depth:integer:=32;addr:integer:=5); port(Clock:in std_logic; Enable:in std_logic; Read:in std_logic; Write:in std_logic; Read_Addr:in std_logic_vector(addr-1 downto 0); Write_Addr: in std_logic_vector(addr-1 downto 0); Data_in: in std_logic_vector(width-1 downto 0); Data_out: out std_logic_vector(width-1 downto 0)); end SRAM; architecture behav of SRAM is type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram:ram_type; begin process(clock,read) begin if(clock'event and clock='1') then if enable='1' then if read='1' then data_out<=tmp_ram(conv_integer(read_addr)); else data_out<=(data_out'range=>'Z'); end if; end if; end if; end process; process(clock,write) begin if(clock'event and clock='1') then if enable='1' then if write='1' then tmp_ram(conv_integer(write_addr))<=data_in; end if; end if; end if; end process; end behav; |
i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM. pls help me to find the error.
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Edited by Moderator
vhdl newbie wrote: > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; Why do you use obsolete librarys? Link: http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector
... However, these packages are NOT standard, and different vendors have different and mutually incompatible versions. Also, there are naming clashes when some of these packages are used together. So, it is recommended that numeric_bit or numeric_std be used in preference to these non-standard packages. |
> i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM.
Beside the librarys the code looks ok. Did you restart your simulation?
How did you recognize the non-functionality?
Duke
vhdl newbie wrote: > process(clock,read) > process(clock,write) These processes are synchronous and therefore only dependent on the clock. So read and write are too much in the sensitivity lists... > depth:integer:=32; addr:integer:=5 These two values are relatives to themselves. So it would be enough to define one of them, then the other can be calculated: type ram_type is array (0 to (2**addr)-1) of ... > i wrote this to create a 4*32 RAM but when i simulate i get a 4*4 RAM. How did you find this out?
1.It is advisable to perform a write cycle first and then read the data ad the data will be in undefined state if you read first. 2. There is no need for 3 parameters(width, depth, addr.). Two are enough. And data_in and data_out must be (depth - 1 downto 0) if you want a 4*32 RAM. If you declare them as (width - 1 downto 0), a 4*4 RAM will be created. In your code, you can remove the width parameter. Depth and addr. are enough. --Regards
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