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Forum: FPGA, VHDL & Verilog Timing Measure Module With RGB Inputs


von Nitish (Guest)


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Hi all

I have a Timing measure module which Outputs a Text File with the 
following :
(VHDL)

Signal            Unit
pixel clock       ps
pixel clock freq  Hz
h_frontporch      pixel clock
h_back porch     pixel clock
h_pulse width     pixel clock
hsync             pixel clock
vsync                hsync
v_frontporch     hsync
v_back porch     hsync
v_pulsewidth     hsync


The input is RGB data (27 downto 0) which includes p_clk , de , 
hsync,vsync , and rgb (each 8 bits)

Please help me to find the logic with these Inputs. Thanks all.

von Lothar M. (lkmiller) (Moderator)


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Nitish wrote:
> I have a Timing measure module
Pls show your VHDL code.

> I have a Timing measure module which Outputs a Text File with the
> following :
So this module is intended only for simulation?

von Nitish (Guest)


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VHDL Code :
1
architecture timing_measure_arc of timing_measure is
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  constant C_CLK_PERIOD  : time := 30 ns ;
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   -- Signals -----------------------------------------------------------------
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  signal de_set_reg : natural ;
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  signal de_reset_reg : natural ;
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  signal hsync_reg : natural ;
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  signal vsync_reg : natural ;
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  signal hfp_reg :natural ;
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  signal hbp_reg :natural ;
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  signal hpw_reg :natural ;
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  signal vfp_reg :natural ;
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  signal vbp_reg :natural ;
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  signal vpw_reg :natural ;
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  alias p_clk is rgb_mux_data (27);
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  alias de_t is rgb_mux_data (26);
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  alias hsync_t is rgb_mux_data (25);
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  alias vsync_t is rgb_mux_data (24);
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  alias rgb_mux_data(23 downto 0) is rgb_mux_data (23 downto 0);  
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   begin
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   -- Asynchrouns Assignments ---------------------------------------------------
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   -- Synchrouns Assignments ---------------------------------------------------- 
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  t_pclk   <= pclk_reg ;
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  de_set   <= de_set_reg ;
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  de_reset <= de_reset_reg ;
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  hsync    <= hsync_reg ;
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  vsync    <= vsync_reg ;
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  h_fp     <= hfp_reg;
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  h_pb     <= hbp_reg;
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  h_pw     <= hpw_reg;
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  v_fp     <= vfp_reg;
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  v_pb     <= vbp_reg;
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  v_pw     <= vpw_reg;
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   -- Processes -----------------------------------------------------------------
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  p_timing_measure : process (reset,p_clk)
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   begin 
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    if reset = '1' then
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      f_pclk      <= '0';
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      t_pclk      <= '0';
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      de_set      <= '0';
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      de_reset    <= '0';
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      h_fp        <= '0';
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      h_pb        <= '0';
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      h_pw        <= '0';
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      hsync       <= '0';
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      v_fp        <= '0';
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      v_pb        <= '0';
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      v_pw        <= '0';
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      vsync       <= '0';
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      de_set_reg <= 0;
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      de_reset_reg <= 0;
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      hsync_reg <= 0;
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      vsync_reg <= 0;
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      hfp_reg<= 0;
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      hbp_reg<= 0;
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      hpw_reg<= 0;
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      vfp_reg<= 0;
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      vbp_reg<= 0;
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      vpw_reg<= 0;
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    elsif reset = '0'  then 
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      if rising_edge(p_clk) then  
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       t_pclk <= C_CLK_PERIOD * 1000 ;
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       f_pclk <= (1/t_pclk) * 1000000 ;
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      if( de_t = '1' and rising_edge(p_clk)) then 
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          loop
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          de_set_reg := de_set_reg +1 ;
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          end loop ;
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      else 
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          loop
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          de_reset_reg := de_reset_reg + 1 ;
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          end loop ;
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      if (hsync_t = '0' and rising_edge(p_clk)) then 
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        loop
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          hsync_reg := hsync_reg +1 ; 
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        end loop ;
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      end if ;
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      if(vsync_t = '0' and falling_edge (hsync_t) ) then
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         loop
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          vsync_reg := vsync_reg +1 ;
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         end  loop ;
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      end if ;
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      wait until(de_t = 0)
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        while (hsync_t = 1) loop
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         wait until rising_edge(p_clk) ;
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           hfp_reg := hfp_reg + 1 ;
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         end loop ;
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      wait until(hsync_t = 1)
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        while (de_t = 0) loop
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         wait until rising_edge(p_clk) ;
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           hbp_reg := hbp_reg + 1 ;
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         end loop ;     
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      if (de_t = 0)     
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        wait until(hsync_t = 0)
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          while (hsync_t= 0) loop
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            wait until rising_edge(p_clk) ;
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             hpw_reg := hpw_reg + 1 ;
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          end loop ;        
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      end if ;
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      wait until(de_t = 0)
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        while (vsync_t = 1) loop
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         wait until falling_edge(hsync_t) ;
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           vfp_reg := vfp_reg + 1 ;
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         end loop ;  
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      wait until(vsync_t = 1)
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        while (de_t = 0) loop
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         wait until falling_edge(hsync_t) ;
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           vbp_reg := vbp_reg + 1 ;
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         end loop ;
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      if (de_t = 0)     
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        wait until(vsync_t = 0)
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          while (vsync_t= 0) loop
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            wait until falling_edge(hsync_t) ;
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             vpw_reg := vpw_reg + 1 ;
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          end loop ;        
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      end if ;  
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    end if;
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  end process p_timing_measure ;

Yes for now, its only  for simulation

: Edited by Admin

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