Timing Measure Module With RGB Inputs

architecture timing_measure_arc of timing_measure is

  constant C_CLK_PERIOD  : time := 30 ns ;

   -- Signals -----------------------------------------------------------------

  signal de_set_reg : natural ;

  signal de_reset_reg : natural ;

  signal hsync_reg : natural ;

  signal vsync_reg : natural ;

  signal hfp_reg :natural ;

  signal hbp_reg :natural ;

  signal hpw_reg :natural ;

  signal vfp_reg :natural ;

  signal vbp_reg :natural ;

  signal vpw_reg :natural ;

  alias p_clk is rgb_mux_data (27);

  alias de_t is rgb_mux_data (26);

  alias hsync_t is rgb_mux_data (25);

  alias vsync_t is rgb_mux_data (24);

  alias rgb_mux_data(23 downto 0) is rgb_mux_data (23 downto 0);  

   begin

   -- Asynchrouns Assignments ---------------------------------------------------

   -- Synchrouns Assignments ---------------------------------------------------- 

  t_pclk   <= pclk_reg ;

  de_set   <= de_set_reg ;

  de_reset <= de_reset_reg ;

  hsync    <= hsync_reg ;

  vsync    <= vsync_reg ;

  h_fp     <= hfp_reg;

  h_pb     <= hbp_reg;

  h_pw     <= hpw_reg;

  v_fp     <= vfp_reg;

  v_pb     <= vbp_reg;

  v_pw     <= vpw_reg;

   -- Processes -----------------------------------------------------------------

  p_timing_measure : process (reset,p_clk)

   begin 

    if reset = '1' then

      f_pclk      <= '0';

      t_pclk      <= '0';

      de_set      <= '0';

      de_reset    <= '0';

      h_fp        <= '0';

      h_pb        <= '0';

      h_pw        <= '0';

      hsync       <= '0';

      v_fp        <= '0';

      v_pb        <= '0';

      v_pw        <= '0';

      vsync       <= '0';

      de_set_reg <= 0;

      de_reset_reg <= 0;

      hsync_reg <= 0;

      vsync_reg <= 0;

      hfp_reg<= 0;

      hbp_reg<= 0;

      hpw_reg<= 0;

      vfp_reg<= 0;

      vbp_reg<= 0;

      vpw_reg<= 0;

    elsif reset = '0'  then 

      if rising_edge(p_clk) then  

       t_pclk <= C_CLK_PERIOD * 1000 ;

       f_pclk <= (1/t_pclk) * 1000000 ;

      if( de_t = '1' and rising_edge(p_clk)) then 

          loop

          de_set_reg := de_set_reg +1 ;

          end loop ;

      else 

          loop

          de_reset_reg := de_reset_reg + 1 ;

          end loop ;

      if (hsync_t = '0' and rising_edge(p_clk)) then 

        loop

          hsync_reg := hsync_reg +1 ; 

        end loop ;

      end if ;

      if(vsync_t = '0' and falling_edge (hsync_t) ) then

         loop

          vsync_reg := vsync_reg +1 ;

         end  loop ;

      end if ;

      wait until(de_t = 0)

        while (hsync_t = 1) loop

         wait until rising_edge(p_clk) ;

           hfp_reg := hfp_reg + 1 ;

         end loop ;

      wait until(hsync_t = 1)

        while (de_t = 0) loop

         wait until rising_edge(p_clk) ;

           hbp_reg := hbp_reg + 1 ;

         end loop ;     

      if (de_t = 0)     

        wait until(hsync_t = 0)

          while (hsync_t= 0) loop

            wait until rising_edge(p_clk) ;

             hpw_reg := hpw_reg + 1 ;

          end loop ;        

      end if ;

      wait until(de_t = 0)

        while (vsync_t = 1) loop

         wait until falling_edge(hsync_t) ;

           vfp_reg := vfp_reg + 1 ;

         end loop ;  

      wait until(vsync_t = 1)

        while (de_t = 0) loop

         wait until falling_edge(hsync_t) ;

           vbp_reg := vbp_reg + 1 ;

         end loop ;

      if (de_t = 0)     

        wait until(vsync_t = 0)

          while (vsync_t= 0) loop

            wait until falling_edge(hsync_t) ;

             vpw_reg := vpw_reg + 1 ;

          end loop ;        

      end if ;  

    end if;

  end process p_timing_measure ;