Forum: FPGA, VHDL & Verilog Control shift registers with FPGA

von Joserra (Guest)

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Hi all, I am new here. I tell you my problem. I have been now several 
days trying to figure it out how to control shift registers SIPO 74LS164 
with my FPGA. I am doing a clock, displaying hours, minutes and seconds 
with NIXIE tubes. What I need to do is to send each second, 24 bits, and 
remain those 24 bits displaying in the NIXIE tubes during the second, 
till the new second comes and new 24 bits are sent. Maybe this is a 
stupid question but I don't know how to produce my clock signal and my 
serial output to control this ICs.

I already have a vector of 24 bits and the schematic of how cascading 
these ICs so that's not the problem. I think you get which my problem 

Please if somebody can help me would be so so great!

Thank you very much


von FPGA-Takt (Guest)

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what HDL do you use?
In Verilog I would try something like this (prob. with errors and not a 
good style)

module( start, stop, secminhour, clk, clkout, dataout);

input start, secminhour, clk;
output dataout, clkout;

reg stop = 1'b1;
reg[0:3] cnt = 4'b0000;

wire[0:23] secminhour = 24'b0;
wire start;
wire clk;
wire clkout;
wire dataout;

assign dataout = secminhour[cnt];
assign clkout = (stop == 1'b0) ? clk : 0;

always @(posedge clk) begin

  if (start = 1'b0) begin
    cnt <= 4'b0000;
    stop <= 1'b0;
  end else begin
    cnt <= cnt + 1;
    if (cnt >= 23) begin
      cnt <= 4'b0000;
      stop <= 1'b1;



U also need a StateMachine to controll this, something like generate 
Data, set start from low to high, wait till stop is set (and the Data 
output was generated) and set start low.

von Joserra (Guest)

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thank you for your answer, I use VHDL, have never used Verilog. I didn't 
think about doing it with a StateMachine, maybe that solve my problem, 
I'll focus the problem from this point of view.

Really, thank you.


von Lothar M. (lkmiller) (Moderator)

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Joserra wrote:
> I didn't think about doing it with a StateMachine, maybe that solve my
> problem
Just keep in mind: even every lousy little conter is a State Machine...

Joserra wrote:
> I don't know how to produce my clock signal and my serial output to
> control this ICs.
Its fairly easy, because no framing is needed for this shift registers. 
So the only thing you must provide is a shift "clock" and stable data on 
the rising edge of this clock...
library IEEE;

entity SPI_Master is  -- SPI-Modus 0: CPOL=0, CPHA=0
    Port ( TX_Data  : in  STD_LOGIC_VECTOR (Length-1 downto 0); -- Sendedaten
           MOSI      : out STD_LOGIC;                           
           SCLK      : out STD_LOGIC;
           TX_Start  : in  STD_LOGIC;
           TX_Active : out STD_LOGIC;
           clk       : in  STD_LOGIC
end SPI_Master;

architecture Behavioral of SPI_Master is
  type   tx_states is (idle,txactive);
  signal txstate    : tx_states := idle;

  signal spiclk : std_logic;
  signal spiclklast: std_logic;

  signal bitcounter    : integer range 0 to Length; -- if bitcounter = Length --> all bits transmitted
  signal tx_reg        : std_logic_vector(Length-1 downto 0) := (others=>'0');

  ------ management FSM --------
  process begin 
     wait until rising_edge(CLK);
     spiclklast <= spiclk;
     case txstate is
       when idle =>
             TX_Active   <= '0';
             bitcounter  <= Length;
             sclk      <= '0';
             if(TX_Start = '1') then 
                stxstate <= txactive; 
                TX_Active   <= '1';
             end if;

       when txactive =>  -- transmit tx_reg
             spiclk <= not spiclk;
             if (bitcounter=0) then -- all bits transmitted -> idle
                spiclk  <= '0';  
                txstate <= idle;
             end if;
             if(spiclk='1') then    
                bitcounter <= bitcounter-1;  
             end if;  
     end case;
  end process;   
  ---- TX Shiftregister -------
  process begin 
     wait until rising_edge(CLK);
     if (spitxstate=idle) then  -- reload when idle
        tx_reg <= TX_Data;
     end if;
     if (spiclk='1' and  spiclklast='0') then -- rising_edge --> assign next data bit
        tx_reg <= tx_reg(tx_reg'left-1 downto 0) & tx_reg(0);
     end if;
  end process;   

  SCLK    <= spiclk;
  MOSI    <= tx_reg(tx_reg'left);
end Behavioral;
(Based on the SPI-Master: 


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