hi guys, first of all i'm new to vhdl my project is to build a microcontroller. my project guide said to search about synthesisable vhdl codes. please help me.

pranoy tm wrote: > first of all i'm new to vhdl > my project is to build a microcontroller. What time schedule do you have? You won't believe it, but in a microcontrollers design there are dumped many man-years of work. And those guys are professionals, not beginners! > my project guide said to search about synthesisable vhdl codes. Thats a good idea if you want a real uC running on a FPGA. > please help me. Whats your question? A little hint: start with a blinking LED, then a chasing light, and so on...

Well, then let´s start with the core of your microcontroller. http://en.wikipedia.org/wiki/LEON too complicated?? then.. Lothar Miller wrote: > start with a blinking LED, then a chasing light, and so > on...

Lothar Miller wrote: > A little hint: start with a blinking LED, then a chasing light, and so > on... Hello, Yes I think the right way is to start with little things. But a processor also consists of easy parts. So first start to learn how to describe: - Multiplexers - combinatorial Logic - An ALU should be possible - State Machines At the moment I am writing a simple CPU in VHDL At the moment it is in process but if you want to you can look ath the source. http://www.blog-tm.de/?p=80

guys first of all it's a 4 bit microcontroller with just 8 basic instructions(+,-,and,or,xor,...). I have done some basic programs like MUX,DEMUX,full adder,carry look ahead adder,decoder,encoder,2's complement,counter I used modelsim as a simulator. i also designed a simple alu. MY QUESTION IS i wrote the alu with statements like c=a+b; can i do like this if i'm to run it on an actual FPGA?

>> i wrote the alu with statements like >> >> c=a+b; Forget variables and use signals, if you work on real hardware. So I think, you have to restart everything.

pranoy tm wrote: > i wrote the alu with statements like > c=a+b; This is no VHDL statement. > can i do like this if i'm to run it on an actual FPGA? Yes you can use +,-,* without any restrictions. But if you want to implement a / then you have to start thinking... BTW: you can read such basic things in almost every new book about "VHDL for FPGAs". > I have done some basic programs VHDL is NOT a programming language! I would say that you have done some basicdesignson a FPGA.

1 | library ieee; |

2 | use ieee.std_logic_1164.all; |

3 | use ieee.std_logic_unsigned.all; |

4 | entity alu_ent is |

5 | port( |

6 | x,y:in std_logic_vector(3 downto 0); |

7 | a:in std_logic_vector(2 downto 0); |

8 | z:out std_logic_vector(3 downto 0) |

9 | ```
);
``` |

10 | end alu_ent; |

11 | architecture alu_arch of alu_ent is |

12 | ```
begin
``` |

13 | process(x,y,a) |

14 | ```
begin
``` |

15 | case a is |

16 | when "000"=>z<=x+y; |

17 | when "001"=>z<=x-y; |

18 | when "010"=>z<=not(x); |

19 | when "011"=>z<=x and y; |

20 | when "100"=>z<=x or y; |

21 | when "101"=>z<=x xor y; |

22 | when others=> z<="XXXX"; |

23 | end case; |

24 | |

25 | |

26 | end process; |

27 | end alu_arch; |

can i execute this on an actual FPGA?

vhdl newbie wrote: > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > entity alu_ent is > port( > x,y:in std_logic_vector(3 downto 0); > a:in std_logic_vector(2 downto 0); > z:out std_logic_vector(3 downto 0) > ); > end alu_ent; > architecture alu_arch of alu_ent is > begin > process(x,y,a) > begin > case a is > when "000"=>z<=x+y; > when "001"=>z<=x-y; > when "010"=>z<=not(x); > when "011"=>z<=x and y; > when "100"=>z<=x or y; > when "101"=>z<=x xor y; > when others=> z<="XXXX"; > end case; > > > end process; > end alu_arch; > > can i execute this on an actual FPGA? Yes you can do this on an actual fpga. But the others statement should result in a defined state like z<= x+y or z <= "0000" Scince an alu is combinatorial you do not need a clock here but at some point in the design. best regards Tobias

vhdl newbie wrote: > use ieee.std_logic_unsigned.all; > when "000"=>z<=x+y; > when "001"=>z<=x-y; Here you should implement any kind ofrolloverhandling (in case of overflow or underflow)...

vhdl newbie wrote: > can i execute this on an actual FPGA? No, you cannot. Because VHDL ist notexecutedon an FGPA. VHDL describes hardware.

thank you all. :) TM wrote: > Yes you can do this on an actual fpga. But the others statement should > result in a defined state like z<= x+y or z <= "0000" what should i do to get high impedance output? Lothar Miller wrote: >> when "000"=>z<=x+y; >> when "001"=>z<=x-y; > Here you should implement any kind of rollover handling (in case of > overflow or underflow)... how can i get the carry? should i use a 4 bit adder instead of the '+' sign?

vhdl newbie wrote: > what should i do to get high impedance output? (Why) do you need high impedance output? >>> when "000"=>z<=x+y; >>> when "001"=>z<=x-y; >> Here you should implement any kind of rollover handling (in case of >> overflow or underflow)... > how can i get the carry? Think a little! And the add one leading bit to recognize overflow/underflow... > should i use a 4 bit adder instead of the '+' sign? What will you gain if you do so?