synthesisable vhdl codes

pranoy tm wrote:
> first of all i'm new to vhdl
> my project is to build a microcontroller.
What time schedule do you have?
You won't believe it, but in a microcontrollers design there are dumped 
many man-years of work. And those guys are professionals, not beginners!

> my project guide said to search about synthesisable vhdl codes.
Thats a good idea if you want a real uC running on a FPGA.

> please help me.
Whats your question?

A little hint: start with a blinking LED, then a chasing light, and so 
on...

guys

first of all it's a 4 bit microcontroller with just 8 basic 
instructions(+,-,and,or,xor,...).

I have done some basic programs like MUX,DEMUX,full adder,carry look 
ahead adder,decoder,encoder,2's complement,counter

I used modelsim as a simulator.

i also designed a simple alu.

MY QUESTION IS

i wrote the alu with statements like

c=a+b;

can i do like this if i'm to run it on an actual FPGA?

pranoy tm wrote:
> i wrote the alu with statements like
> c=a+b;
This is no VHDL statement.

> can i do like this if i'm to run it on an actual FPGA?
Yes you can use +,-,* without any restrictions. But if you want to 
implement a / then you have to start thinking...

BTW: you can read such basic things in almost every new book about "VHDL 
for FPGAs".

> I have done some basic programs
VHDL is NOT a programming language!
I would say that you have done some basic designs on a FPGA.

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library ieee;

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    use ieee.std_logic_1164.all;

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    use ieee.std_logic_unsigned.all;

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    entity alu_ent is

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        port(

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            x,y:in std_logic_vector(3 downto 0);

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            a:in std_logic_vector(2 downto 0);

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            z:out std_logic_vector(3 downto 0)

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            );

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        end alu_ent;

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        architecture alu_arch of alu_ent is

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        begin

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        process(x,y,a)

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        begin

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            case a is

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                when "000"=>z<=x+y;

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                when "001"=>z<=x-y;

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                when "010"=>z<=not(x);

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                when "011"=>z<=x and y;

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                when "100"=>z<=x or y;

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                when "101"=>z<=x xor y;

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                when others=> z<="XXXX";

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            end case;

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    end process;

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    end alu_arch;

can i execute this on an actual FPGA?

vhdl newbie wrote:
> use ieee.std_logic_unsigned.all;
>                 when "000"=>z<=x+y;
>                 when "001"=>z<=x-y;
Here you should implement any kind of rollover handling (in case of 
overflow or underflow)...

thank you all. :)

TM wrote:
> Yes you can do this on an actual fpga. But the others statement should
> result in a defined state like z<= x+y or z <= "0000"

what should i do to get high impedance output?



Lothar Miller wrote:
>>                 when "000"=>z<=x+y;
>>                 when "001"=>z<=x-y;
> Here you should implement any kind of rollover handling (in case of
> overflow or underflow)...


how can i get the carry?
should i use a 4 bit adder instead of the '+' sign?

vhdl newbie wrote:
> what should i do to get high impedance output?
(Why) do you need high impedance output?


>>> when "000"=>z<=x+y;
>>>  when "001"=>z<=x-y;
>> Here you should implement any kind of rollover handling (in case of
>> overflow or underflow)...
> how can i get the carry?
Think a little!
And the add one leading bit to recognize overflow/underflow...

> should i use a 4 bit adder instead of the '+' sign?
What will you gain if you do so?