Regarding DAD instruction in 8085

Guest #3324884
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DAD is a single byte instruction. So there is only one ALE pulse.

HLT is fetch cycle followed by 1 or more wait cycles. Once HLT is 
executed it inserts wait states in every clock period until the chip is 
reset or an interrupt occurs. Address and data bus are floating.
OP (Company: DEI) #3325481
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Gordon Shumway wrote:
> Sometimes I wonder why people don't use the internet search
> capabilities...
> I just entered "8085 instruction set machine cycle" and I received the
> following catch...
>
> 
http://www.phy.davidson.edu/fachome/dmb/py310/EMAC_Primer/8085.InstructionSet.full.pdf
>
> Gordon Shumway aka TOKABLN

Sir
I know the DAD instruction is one byte instruction and taking three 
machine cycles. But I want to know whether ALE high twice in opcode 
fetch cycle or not. Can any idea of its timing diagram.(or any link)

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