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Forum: FPGA, VHDL & Verilog Trying to compile a VHDL code using GHDL but I am getting a weird error


von Ahmed Yousif (Guest)


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Hi there,

I have written a code of an FSM using VHDL and used GHDL to compile it.

The error that is prompting is

hello.vhdl:25:50: "<=" or ":=" expected instead of then.

I have attached the file of the code.

Here I paste it too:
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity ex19 is
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  Port(
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    X, SET: in std_logic;
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    clk:in std_logic;
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    Y: out std_logic_vector (0 to 1);
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    Z2: out std_logic);
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end ex19;
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architecture ex19arc of ex19 is
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  type stateType is(ST0, ST1, ST2);
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  Signal PS, NS: StateType;
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  begin
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  sync_proc: process (CLK, NS, SET)
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    Begin
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      If (SET = '1') then
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      PS <= ST2;
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      elseif (rising_edge(clk)) then
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      PS <= NS;
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      else PS <= PS;
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      end if;
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    End process sync_proc;
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  comb_proc: process (PS,x)
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    Begin
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    case PS is
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      when ST0 =>
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        Z2 <= '0';
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        if (x = '0') then
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        NS <= ST0;
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        else NS <= ST1;
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        end if;
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      when ST1 =>
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        Z2 <= '0';
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        if (x = '0') then
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        NS <= ST0;
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        else
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        NS <= ST2;
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        end if;
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      when ST2 =>
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        if (x = '0') then
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        NS <= ST0;
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        Z2 <= '0';
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        else
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        NS <= ST2;
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        Z2 <= 1;
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        end if;
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    end case;
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    end process;
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  with PS select
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    Y <=  "00" when ST0,
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      "10" when ST1,
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      "11" when ST2,
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      "00" when others;
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end ex19arc;

von Olga (Guest)


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It's not a weird error. It's absolute clear error. If you read first 
chapter of your VHDL book or script, damn it!

von dose (Guest)


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elseif  is not a vhdl reserved word

try

elsif

von Lothar M. (lkmiller) (Moderator)


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dose wrote:
> elseif  is not a vhdl reserved word
With a editor capable of syntax highlighting (or even up there in the 
posted VHDL code) this can be seen by the different color of the 
keyword.

After having corrected the error and indented the source code there 
remains one big question:
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      If (SET = '1') then
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          PS <= ST2;
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      elsif rising_edge(clk) then
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          PS <= NS;
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      else 
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          PS <= PS;
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      end if;
Where the heck did you see that kind of descritpion with an else clause 
after a rising_edge?

von Ahmed Yousif (Guest)


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Thanks guys.

I totally forgot about the "e" in elseif.

The error was on a gcc compiler.

von Ahmed Yousif (Guest)


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Hi Guys,

Another questions are:

1. How can I control the ports using ghdl? Can I change the values of 
the inputs? I need this to test the program.

2. How can I write the output on the screen?

von Lothar M. (lkmiller) (Moderator)


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Ahmed Yousif wrote:
> 1. How can I control the ports using ghdl? Can I change the values of
> the inputs? I need this to test the program.
Just flip your book (the one from the second post) over to the chapter 
"vhdl testbench"...

Its fairly easy: you write a VHDL entity without any ports in the entity 
declaration. Inside this module you invoke your ex19 as a component and 
additionally implement your stimuli signals for that module.

See this (its German, but maybe google translator helps out):
http://www.lothar-miller.de/s9y/archives/80-Hello-World!.html

BTW: you should name the entity not very different than the file.
Its fairly confusing to find a "ex19" in a "hello.vhdl"...

von Ahmed Yousif (Guest)


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Hi,

Thanks for the help. I will read more about the testbench.

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