Hi there, I have written a code of an FSM using VHDL and used GHDL to compile it. The error that is prompting is hello.vhdl:25:50: "<=" or ":=" expected instead of then. I have attached the file of the code. Here I paste it too:
library IEEE; use IEEE.std_logic_1164.all; entity ex19 is Port( X, SET: in std_logic; clk:in std_logic; Y: out std_logic_vector (0 to 1); Z2: out std_logic); end ex19; architecture ex19arc of ex19 is type stateType is(ST0, ST1, ST2); Signal PS, NS: StateType; begin sync_proc: process (CLK, NS, SET) Begin If (SET = '1') then PS <= ST2; elseif (rising_edge(clk)) then PS <= NS; else PS <= PS; end if; End process sync_proc; comb_proc: process (PS,x) Begin case PS is when ST0 => Z2 <= '0'; if (x = '0') then NS <= ST0; else NS <= ST1; end if; when ST1 => Z2 <= '0'; if (x = '0') then NS <= ST0; else NS <= ST2; end if; when ST2 => if (x = '0') then NS <= ST0; Z2 <= '0'; else NS <= ST2; Z2 <= 1; end if; end case; end process; with PS select Y <= "00" when ST0, "10" when ST1, "11" when ST2, "00" when others; end ex19arc;
It's not a weird error. It's absolute clear error. If you read first chapter of your VHDL book or script, damn it!
elseif is not a vhdl reserved word try elsif
dose wrote: > elseif is not a vhdl reserved word With a editor capable of syntax highlighting (or even up there in the posted VHDL code) this can be seen by the different color of the keyword. After having corrected the error and indented the source code there remains one big question:
If (SET = '1') then PS <= ST2; elsif rising_edge(clk) then PS <= NS; else PS <= PS; end if;
Where the heck did you see that kind of descritpion with an else clause after a rising_edge?
Thanks guys. I totally forgot about the "e" in elseif. The error was on a gcc compiler.
Hi Guys, Another questions are: 1. How can I control the ports using ghdl? Can I change the values of the inputs? I need this to test the program. 2. How can I write the output on the screen?
Ahmed Yousif wrote: > 1. How can I control the ports using ghdl? Can I change the values of > the inputs? I need this to test the program. Just flip your book (the one from the second post) over to the chapter "vhdl testbench"... Its fairly easy: you write a VHDL entity without any ports in the entity declaration. Inside this module you invoke your ex19 as a component and additionally implement your stimuli signals for that module. See this (its German, but maybe google translator helps out): http://www.lothar-miller.de/s9y/archives/80-Hello-World!.html BTW: you should name the entity not very different than the file. Its fairly confusing to find a "ex19" in a "hello.vhdl"...
Hi, Thanks for the help. I will read more about the testbench.