library IEEE;
use IEEE.std_logic_1164.all;

entity ex19 is
  Port(
    X, SET: in std_logic;
    clk:in std_logic;
    Y: out std_logic_vector (0 to 1);
    Z2: out std_logic);
end ex19;

architecture ex19arc of ex19 is

  type stateType is(ST0, ST1, ST2);
  Signal PS, NS: StateType;

  begin

  sync_proc: process (CLK, NS, SET)
    

    Begin
      If (SET = '1') then
      PS <= ST2;
      elseif (rising_edge(clk)) then
      PS <= NS;
      else PS <= PS;
      end if;
    End process sync_proc;

  comb_proc: process (PS,x)
  
    Begin
    case PS is
      when ST0 =>
        Z2 <= '0';
        if (x = '0') then
        NS <= ST0;
        else NS <= ST1;
        end if;
      when ST1 =>
        Z2 <= '0';
        if (x = '0') then
        NS <= ST0;
        else
        NS <= ST2;
        end if;
      when ST2 =>
        if (x = '0') then
        NS <= ST0;
        Z2 <= '0';
        else
        NS <= ST2;
        Z2 <= 1;
        end if;
      
    end case;
    end process;

  with PS select
    Y <=  "00" when ST0,
      "10" when ST1,
      "11" when ST2,
      "00" when others;
end ex19arc;