library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.NUMERIC_STD.ALL;

use STD.TEXTIO.ALL;

library WORK;

use WORK.pkgg.ALL;

entity scrambler is

    Port ( e : in  STD_LOGIC_VECTOR (29 downto 0);

           Sel : in  STD_LOGIC_VECTOR (3 downto 0);

           s : out  STD_LOGIC_VECTOR (29 downto 0));

end scrambler;

architecture Behavioral of scrambler is

   SIGNAL rst_n :   std_logic;

   SIGNAL clk   :   std_logic;

   SIGNAL dout  :  std_logic_vector(29 downto 0);

    CONSTANT width  : integer     := 30;

    CONSTANT length : integer     := 31;         -- length of the register

    CONSTANT taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2);

           component genlfsr 

           generic (

    width  : integer     := 30;

    length : integer     := 31;         

    taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2)

    );

    port ( 

    rst_n : in  std_logic;

    clk   : in  std_logic;

    dout  : out std_logic_vector(29 downto 0) 

          );

  end component;

bgin

U1: entity work.genlfsr(behavioral) 

    generic map (width => width ,length => length ,taps => taps)

    port map(rst_n => rst_n ,clk => clk ,dout =>dout);

process (dout ) is

   begin

 s(29 downto 29-dout'high) <= dout;

 end process;

end Behavioral;