good morning
I want to program a vhdl code wich work with input , output and selector
pointing a generic component. this component is a registre lfsr each
time it take new parameter generator polynomial
it joined my idea of implementation
And this my first think of code :

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libraryIEEE;

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useIEEE.STD_LOGIC_1164.ALL;

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useIEEE.STD_LOGIC_ARITH.ALL;

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useIEEE.NUMERIC_STD.ALL;

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useSTD.TEXTIO.ALL;

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libraryWORK;

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useWORK.pkgg.ALL;

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entityscrambleris

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Port(e:inSTD_LOGIC_VECTOR(29downto0);

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Sel:inSTD_LOGIC_VECTOR(3downto0);

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s:outSTD_LOGIC_VECTOR(29downto0));

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endscrambler;

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architectureBehavioralofscrambleris

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SIGNALrst_n:std_logic;

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SIGNALclk:std_logic;

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SIGNALdout:std_logic_vector(29downto0);

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CONSTANTwidth:integer:=30;

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CONSTANTlength:integer:=31;-- length of the register

siwar wrote:> So I don't understand how to make a generic registre lfsr with different> value
What do you mean with a "different value"?
Different taps?
siwar wrote:> 12:33siwar wrote:> 13:02> please help me
Please wait some minutes. At least half an hour. This is not a hotline.
And then post your own suggestion of a solution for the desired
component "genlfsr". Then we can discuss the design. But no one is
intended to do all of your job, bcause its your homework...
And additionally: one post is enough! I have deleted the other one.