good morning
I want to program a vhdl code wich work with input , output and selector
pointing a generic component. this component is a registre lfsr each
time it take new parameter generator polynomial
it joined my idea of implementation
And this my first think of code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
library WORK;
use WORK.pkgg.ALL;
entity scrambler isPort ( e : inSTD_LOGIC_VECTOR (29downto0);
Sel : inSTD_LOGIC_VECTOR (3downto0);
s : outSTD_LOGIC_VECTOR (29downto0));
end scrambler;
architecture Behavioral of scrambler isSIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL dout : std_logic_vector(29downto0);
CONSTANT width : integer := 30;
CONSTANT length : integer := 31; -- length of the registerCONSTANT taps : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2);
component genlfsr
generic (
width : integer := 30;
length : integer := 31;
taps : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2)
);
port (
rst_n : instd_logic;
clk : instd_logic;
dout : outstd_logic_vector(29downto0)
);
endcomponent;
bgin
U1: entity work.genlfsr(behavioral)
genericmap (width => width ,length => length ,taps => taps)
portmap(rst_n => rst_n ,clk => clk ,dout =>dout);
process (dout ) isbegin
s(29downto29-dout'high) <= dout;
endprocess;
end Behavioral;

So I don't understand how to make a generic registre lfsr with different
value

siwar wrote:> So I don't understand how to make a generic registre lfsr with different> value
What do you mean with a "different value"?
Different taps?
siwar wrote:> 12:33siwar wrote:> 13:02> please help me
Please wait some minutes. At least half an hour. This is not a hotline.
And then post your own suggestion of a solution for the desired
component "genlfsr". Then we can discuss the design. But no one is
intended to do all of your job, bcause its your homework...
And additionally: one post is enough! I have deleted the other one.