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Forum: FPGA, VHDL & Verilog generic register lfsr


von siwar (Guest)


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good morning
I want to program a vhdl code wich work with input , output and selector 
pointing a generic component. this component is a registre lfsr each 
time it take new parameter generator polynomial

it joined my idea of implementation

And this my first think of code :
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use STD.TEXTIO.ALL;
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library WORK;
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use WORK.pkgg.ALL;
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entity scrambler is
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    Port ( e : in  STD_LOGIC_VECTOR (29 downto 0);
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           Sel : in  STD_LOGIC_VECTOR (3 downto 0);
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           s : out  STD_LOGIC_VECTOR (29 downto 0));
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end scrambler;
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architecture Behavioral of scrambler is
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   SIGNAL rst_n :   std_logic;
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   SIGNAL clk   :   std_logic;
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   SIGNAL dout  :  std_logic_vector(29 downto 0);
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    CONSTANT width  : integer     := 30;
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    CONSTANT length : integer     := 31;         -- length of the register
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    CONSTANT taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2);
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           component genlfsr 
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           generic (
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    width  : integer     := 30;
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    length : integer     := 31;         
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    taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2)
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    );
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    port ( 
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    rst_n : in  std_logic;
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    clk   : in  std_logic;
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    dout  : out std_logic_vector(29 downto 0) 
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          );
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  end component;
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bgin
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U1: entity work.genlfsr(behavioral) 
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    generic map (width => width ,length => length ,taps => taps)
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    port map(rst_n => rst_n ,clk => clk ,dout =>dout);
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process (dout ) is
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   begin
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 s(29 downto 29-dout'high) <= dout;
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 end process;
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end Behavioral;

So I don't understand how to make a generic registre lfsr with different 
value

von siwar (Guest)


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please help me

von Lothar M. (lkmiller) (Moderator)


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siwar wrote:
> So I don't understand how to make a generic registre lfsr with different
> value
What do you mean with a "different value"?
Different taps?

siwar wrote:
> 12:33
siwar wrote:
> 13:02
> please help me
Please wait some minutes. At least half an hour. This is not a hotline.

And then post your own suggestion of a solution for the desired 
component "genlfsr". Then we can discuss the design. But no one is 
intended to do all of your job, bcause its your homework...


And additionally: one post is enough! I have deleted the other one.

von siwar (Guest)


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I apologize for the inconvenience
I'm sorry

von anynomous (Guest)


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you should describe what you want,

i simply cannot imagine what is intended

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