Page 7 shows the output of the CCD:
For every shift cycle you get another signal at the output, which 
relates the number of charges of the photo-cell. the leading and the 
trailing charge-signal (marked as dummy) come from dummy cells, ie. do 
not corrospond to a pixel, so you may ignore them. (well, sometimes this 
pixel are used the generate a "black pixel reference level" but you will 
need a specialized ADC to benefit from this).


 Shortly after shifting-out a single element you shall smaple it from 
you ADC. So you can delaying the shift clock to generate the sample 
clock.

One option could be to operate with an higher clock in fpga say 300 MHz 
when the shift (pixel) clock is 50 MHz. then you have a counters runing 
at 300 MHz, if the counter is counts 0,1,2 shift clock is high, and if 
it counts 1,2,3 sample clock is High.  optimising the phase und pulse 
width of ccd shift gain and sample clock reduce the pixel noise a lot.


OK this is just a sketch, often a look into a datasheet of  a line-ccd
controller (Keyword :"Linear CCD  Driver" ) or of a linear ccd optimised 
ADC
i.e. 
http://www.analog.com/static/imported-files/data_sheets_obsolete/OBSOLETE%20WATERMARK/AD9807.pdf).

Best regards,

Lothar Miller wrote:
> Karl Könner wrote:

> SH ist not the "shift clock", because there is no shift clock at all.
> With the SH pin you only control the shutter "opening"...


page 2, table "pin names", line "SH"  -> reads "Shift gate"


Anyway, every charged coupled device needs a shift signal (sometetime 
(internally, see block "Logic circuitry) generated by (internally) 
overlapping clock signals) to move (shift) the charges over the "bucket 
brigade". Shifting ist "essential" for CCD's, there is no CCD working 
without a "shift-circuitry/clock). (See 
http://en.wikipedia.org/wiki/Charge-coupled_device, search for the term 
"shift" (Ctrl-f))

After "forcing and finishing" this shift by controlling the signals to 
the CD-line,  you have to initiate the sampling of the analog output.


>The process is to "clear" the ccd cells with a pulse on the ICG pin.
>Then with each forth master clock cycle new analog data is output on OS
>(so data rate is 1/4 the master clock).
ACK

It's a bit confusing that there are 2 timing charts (p6/p7). At page 7 
it seems that after every SH-Pulse new data is presented at the signal 
output, where at page 6 there is just a single SH-Pulse.

I am more familiar with image sensor than with liniear sensors

Best regards,