Hi. I'm trying to find out if it's necessary to clock every other
register in, say, a shift register, alternating between the positive
clock transition and the negative clock transition. Something like this
VHDL:
I know this works at lower speeds:
1  if(clk'event and clk='1')then

2  D <= C;

3  C <= B;

4  B <= A;

5  A <= input;

6  end if;

But I wonder if at higher speeds this sort of coding is required:
1  if(clk'event and clk='1')then

2  D <= C;

3  B <= A;

4  end if

5  if(clk'event and clk='0')then

6  C <= B;

7  A <= input;

8  end if;

That way, in my second example, "B" for instance captures it's data in
the middle of "A's" data eye. Is this coding style required above some
speed? If so, does anyone know how to find out what speed or some
approximate?