Hi. I'm trying to find out if it's necessary to clock every other register in, say, a shift register, alternating between the positive clock transition and the negative clock transition. Something like this VHDL: I know this works at lower speeds:
if(clk'event and clk='1')then D <= C; C <= B; B <= A; A <= input; end if;
But I wonder if at higher speeds this sort of coding is required:
if(clk'event and clk='1')then D <= C; B <= A; end if if(clk'event and clk='0')then C <= B; A <= input; end if;
That way, in my second example, "B" for instance captures it's data in the middle of "A's" data eye. Is this coding style required above some speed? If so, does anyone know how to find out what speed or some approximate?
No this not necessary. STA tells you the max. frequency of a synchronous system.
Taylor McCall wrote: > Is this coding style required above some speed? No. Its just nonsense! It additionally doubles the designs frequency, because then you have only the half clock cycle from the rising to the falling edge. And you must be activ on both of them. It will be even worse, if the clock is not 50/50 but 60/40... FPGA flipflops are designed to need no hold time. So it gives you the best timing margin if you set the sample point at the "end" of the clock cycle. Of course your both examples do not give the same result. In the first one you need 4 clocks to see the input at signal D. In the second one only 2 clocks are necessary to transport input to D (thats the virtual clock doubling). Just simulate it... Ottmar wrote: > STA tells you the max. frequency of a synchronous system. Thats correct, but "Static Timing Analysis" is not the answer to the question...
Lothar Miller wrote: > FPGA flipflops are designed to need no hold time. I believe this is the info most useful here. Thank you!