I want an error when I examine my vhdl program with Project NAvigator ISE this is the error : "Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow" please help me thanks
Guest
#3260294
Hi, It seems that your constraint file is not suitable. Do you use a demo board or something like that? Rosa
No I don't use a demo board. what is a constraint file ? how make it ?
Guest
#3260670
What FPGA you are using? Duke
siwar dammak wrote: > what is a constraint file ? Google's not working? https://www.google.com/search?q=constraint+file+xilinx
My type of FPGA is Spartan-3A xc3s700a-4fg484