Dear all, I've got a problem with to_unsigned(). I'm using the code below for a test-bench, but an error occures while simulating the code if using "Enable optimization", or a FATAL error while loading the design. My Code is:
1 | TDinput (line_width-1 downto 0)<= std_logic_vector (to_unsigned(43,line_width)); |
while TDinput is an STD_LOGIC_VECTOR, and line_width is an INTEGER. The error is : # ** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/GenMux/MUX_behav/2/Generic_mux1.vhd(26): (vopt-1144) Value -7 is out of std.standard.natural range 0 to 2147483647. # ** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/GenMux/MUX_behav/2/Generic_mux1.vhd(26): (vopt-1153) Index value -7 is out of index range of ieee.std_logic_1164.std_logic_vector; it is less than 0. Please give me a hint to resolve the problem. THANKS