Dear all, I've got a problem with to_unsigned(). I'm using the code below for a test-bench, but an error occures while simulating the code if using "Enable optimization", or a FATAL error while loading the design. My Code is:
TDinput (line_width-1 downto 0)<= std_logic_vector (to_unsigned(43,line_width));
while TDinput is an STD_LOGIC_VECTOR, and line_width is an INTEGER. The error is : # ** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/GenMux/MUX_behav/2/Generic_mux1.vhd(26): (vopt-1144) Value -7 is out of std.standard.natural range 0 to 2147483647. # ** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/GenMux/MUX_behav/2/Generic_mux1.vhd(26): (vopt-1153) Index value -7 is out of index range of ieee.std_logic_1164.std_logic_vector; it is less than 0. Please give me a hint to resolve the problem. THANKS
try this. x <= to_unsigned(2, x'length);
Meli wrote: > line_width is an INTEGER. Is it a constant integer? What value does it have? Where comes the -7 from? > Please give me a hint to resolve the problem. The problem is not located in the posted line. Pls. attach the complete *.vhdl file...
@ Martin: I've also tried that, but the same error is stucked! @ Lothar Miller : The line_width is a generic integer with the initial value of 8. First, I thought -7 is related to the inital value of the line_width, but as u can see in the code, it doesn't seem like it is related to that. By the way, the whole error comments continues from -7 to -1 !!
Lothar Miller wrote: > Pls. attach the complete *.vhdl file... Meli wrote: > Attached files: > TB.txt *.txt ist not *.vhdl There is a reason why I wrote *.vhdl explicitly: the board software recognizes file types with the file extension, and it supports syntax highlighting for known file types... Meli wrote: > By the way, the whole error comments continues from -7 to -1 !! The problem is not in the posted code. I took it, added the missing component and: it simulates perfect. See the attached files... > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > use IEEE.numeric_std.all; Use the first two or the last one, but never ever all three of them together! Otherwise you can observe strange messages now and then...
Dear Lothar, I didn't know about the borad software, sorry! And thank you for your quick reply. The line u added for the test vectors is not needed since the select line is 3-bit selecting between 0 to 7. But any way, U did really help. Thank u so much. I'm so glad that I visited your site by chance. I'm a fan from now on ;-)
Meli wrote: > The line u added for the test vectors is not needed since the select > line is 3-bit selecting between 0 to 7. Recalculate this once more and you will see: 0..7 are 8 positions. Therefore 8 positions must be initialized (according to your own testbench). And for the highest bit position it is 8*8-1 = 63. You can see this in the Waveform when tsel is 7: the value 12 (i added) is visible on toutput... > Thank u so much. You're welcome... ;-)
Thanks Lothar. Yeh, u'r right. Thanks again and have fun :-D