Hi to all, A homework task I got is to implement a synchronous program that checks a tic tac toe board, which is of n*n size. The program detects if there is a winner ( Are all the elements in a row or column the same) and if so, who is the winner. the information of the content of the board is given by "D_in": 00- blank cell; 01- X; 10- O; 11- end of line The information is inserted in the shift-register method- row by row ( left to right), and when a row ends there's 11/ end of the whole board is represented by "Rst_n" being '0'. The output of the program is given by "Stts: 00- waiting; 01- X wins; 10- O wins; 11- draw The way I chose to implement the exercise is as follows: - final state machine (of D_in) for the row check. - XOR of a last row memory with the current D_in for the column check. The program includes a testbench which checks the following options: - O row win; X row win; O column win; X column win; draw for some reason which I don't manage to get hold of the program doesn't get the output which it is supposed to. any idea why? Attached above is the code and a sketch of the block diagram of the program and the FSM. thanks in advance, Amitai PS I had a simulation error which pointed that there's a problem in the main loop of the program. I decided temporally to get rid of it by changing in line 69 from "C < n" to "C < n-1". (although I didn't manage to understand why is "C < n" out of range)
Amitai Weil wrote: > I decided temporally to get rid of it by changing in > line 69 from "C < n" to "C < n-1". The problem is not the line 69, the problem is that in this line the signal C will get the value n for one cycle. And then you have an access to changed_chk(C) which is limited to (n-1)... Do you only want to run this whole thing in simulation or must ist be synthesizeable? If it must be synthesizeable (because of the clock): did you ever see something like this in any synthesizeable VHDL description all around the world?
for i in 0 to n-1 loop -- row loop if (clk'event and clk='1') then
No? And why? You have never seen such a thing, because this is simply not synthesizeable. Let me say it this way: a loop in VHDL (and also Verilog) is something completely different than a loop in an programming language (i should add at least 5 or 10 exclamation marks at the end of this sentence)!!! And also the reset will not work as expected, because the later assignments to signals in the process will override the reset value (here for example tmp_stts):
if (Rst_n='0') then -- reset operation cur_st <= IDLE; memory_last_row <= (others => '0'); C <= 0; tmp_Stts <= "00"; end if; if i = n-1 and tmp_Stts = "00" then -- COULMN check if changed_chk(C) = '0' and D_in = "01" then tmp_Stts <= "01"; elsif changed_chk(C) = '0' and D_in = "10" then tmp_Stts <= "10"; end if; end if; if D_in = "11" and tmp_Stts = "00" then -- ROW check if cur_st = X_chk then tmp_Stts <= "01"; elsif cur_st = O_chk then tmp_Stts <= "10";
For signals in processes you must keep in mind: the last assignment wins! > - final state machine (of D_in) for the row check. Hmm, isn't that a "finite state machine" usually? A "final" state machine is the "last and ultimate" state machine ever... This here will never be true, becaue D_in is (according to your test bench" never "0-":
case D_in is when "0-" =>
Here D_in must be exactly "0-", if you only want to check the left bit of D_in then you must write:
case D_in(1) is when '0' =>
Thanks for all the comments, The intension in this exercise is to make a simulation by modelsim and that's why the clock is part of the process. I have made the changes in the part of the FSM ( -1 to D_in(1)), so did i move the reset to the end of the main process. As far as I know the commands in a process run by their order and therefor I still don't see why the output isn't as expected I attached above the DO file which runs the program in modelsim, a capture of the wave-form of the simulated and synthesized program by modelsim and the renewed program. Amitai
Amitai Weil wrote: > The intension in this exercise is to make a simulation by modelsim and > that's why the clock is part of the process. There is no clock needed for the checking of the matrix. See here my TicTacToe checking algo. You must of course add a bit more to read in data...
The idea of the program is that a user ( whom controls "D_in" and "Rst_n") inserts the matrix row by row, in a left to right order. The end of a line is announced by D_in = "11" and an end of the whole matrix is announced by Rst_n = '0'; In case there's a winner found during the check process the output should stay the same till the end of the check ( only one winner is possible). if theres no winner in the check process the output Stts will by "11" At first I want to check only it theres a winner by checking the rows, and leave aside in the meantime the columns check. In the testbench I need to check these 5 options: 1. O row wins 2. X row wins 3. O column wins 4. X column wins 5. draw At the first, second and last options the input is correct. however in the rest there's a problem and the input is incorrect. I assume the problem is somehow connected to the FSM, and that for some reason the next state in the FSM is depended on the current state. any idea what's the problem? I attached above the a capture of the wave-form of the simulated and synthesized program by modelsim and the renewed program. Amitai P.S. Thanks for the program and the effort but I need to do actualize the program in the framework of the conditions brought above.
I managed to implement a program which checks the rows of the array, now for the columns... I want to implement An array of FSM situations, so that for each column that I'm checking presently they will be a memory of the last row same column to compare to. that's because the information of the X/0 table is given by the input of the user (testbench) and I don't want to save all of it. ( if the board is n*n and n=999999 .....) so I wrote as follows: type C_state_type is (IDLE_C, X_chk_C, O_chk_C, tmp_draw_C); signal cur_st_C, nxt_st_C is array (1 to n) of C_state_type; any idea if this can be implemented somehow? If so, what should I change? because modelsim doesn't agree to this. Thanks, Amitai
Amitai Weil wrote: > any idea if this can be implemented somehow? To shorten things: I did a little bit coding in the lunch break. Have a look at it...
A Full design and Verilog code for Tic Tac Toe game as follow: http://www.fpga4student.com/2017/06/tic-tac-toe-game-in-verilog-and-logisim.html There are more FPGA projects on FPGA4student.com: http://www.fpga4student.com/ http://www.fpga4student.com/p/fpga-projects.html http://www.fpga4student.com/p/verilog-project.html http://www.fpga4student.com/p/vhdl-project.html