Design the baud rate synchronizes transmitter and receiver of UART

Design the baud rate synchronizes transmitter and receiver of UART. 
Clock divider in UART play important role as it provides appropriate 
frequency clock as per required by the baud rate. The calculation of 
baud rate divider required following formula:
No. of Counts= (FPGA Freq/Baud Rate)/2
Design a module which takes four Baud Rates 600,1200,2400,4800 and 
provide the divided clock freq. accordingly.


module ClockDivider(input Clk,output BClk,input [1:0]BSel);
//BClk-Baud Clock
//Clk-input Clock // BSel-Baud Rate Select, 00-600, 01-1200,10-2400, 
11-4800
Endmodule


how should i write the verilog code for this....
Please help me