Hi to all,

A homework task I got is to create a component which receives
positive numbers and gives the output of A+B-C+D-E...

I got a few error's which seem to be all connected to each other,
but I don't manage to understand what the problem is.

The code is:

 library ieee;
use ieee.std_logic_1164.all;

-- mux2to1 Component ----
-------------
entity mux2_1 is port
       (d0    : in  integer;
    d1    : in  integer;
    sel   : in  bit;
    d_out : out integer);
end entity;

architecture mux2_1_arc of mux2_1 is

 begin
 with sel select
   d_out <= d0 when '0',
            d1 when '1';
end architecture;
--------------------

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;

-- d_ff for result Component ----  (integer input)
-------------
entity d_ff_res is port
     (clk_ff        : in std_logic;
        d_ff_in_res   : in integer;
    d_ff_out_res  : out integer);
end entity;

architecture w_sens_list of d_ff_res is

begin
  process (clk_ff)
    begin
    if clk_ff'event and clk_ff='1' then
      d_ff_out_res <= d_ff_in_res;
    end if;
  end process;

end architecture;
----------------------

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;

-- d_ff for mux Component ----    (bit input)
-------------
entity d_ff_mux is port
     (clk_ff        : in std_logic;
        d_ff_in_mux   : in bit;
    d_ff_out_mux  : out bit);
end entity;

architecture w_sens_list of d_ff_mux is

begin
  process (clk_ff)
    begin
    if clk_ff'event and clk_ff='1' then
      d_ff_out_mux <= d_ff_in_mux;
    end if;
  end process;

end architecture;
----------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use std.env.all;

-- main Component  ---
-----------------------
entity taylor_seq is generic (n : positive := 5);
  port (D_in  : in  integer;
        Rst_n : in  std_logic;
    clk   : in  std_logic;
    RES   : out integer );
end entity;

architecture arc_taylor_se of taylor_seq is

  signal mux_o, last_RES, tran_RES  : integer;
  signal sel_mux, rev_sel : bit;
  constant CCT      : time := 10 ns;

  begin
    last_RES <= 0;
  mux_o    <= 0;
  RES      <= 0;
  sel_mux  <= '0';
  tran_RES <= 0;
  Rst_n <= '1';
  rev_sel <= NOT sel_mux;
  clk <= not (clk) after CCT / 2;

  my_mux : entity work.mux2_1 port map (
        d0       => D_in,
        d1       => D_in,
        sel      => sel_mux,
        d_out    => mux_o);

  MUX_DFF : entity work.d_ff_mux port map (
        d_ff_in_mux    => rev_sel,
        d_ff_out_mux   => sel_mux,
        clk_ff         => clk);

  RES_DFF : entity work.d_ff_res port map (
    d_ff_in_res    => tran_RES,
    d_ff_out_res   => last_RES,
    clk_ff         => clk);

  FAs_generator: for i in 1 to n generate

      process (clk)
     begin
      if rising_edge (clk) then
      if Rst_n='1' then
        if sel_mux = '1' then
          tran_RES <= last_RES+mux_o;
        else
          tran_RES <= last_RES-mux_o;
        end if;

        RES <= tran_RES;

      else        -- Rst_n= 0
       RES   <= 0;
       Rst_n <= '1';
      end if;
      end if;
    end process;
  end generate;
end architecture;



and the compiler's response is:

 ** Error: ex4.vhd(98): Cannot drive signal 'Rst_n' of mode IN.
# ** Error: ex4.vhd(100): Cannot drive signal 'clk' of mode IN.
# -- Loading entity mux2_1
# -- Loading entity d_ff_mux
# -- Loading entity d_ff_res
# ** Error: ex4.vhd(134): Cannot drive signal 'Rst_n' of mode IN.
# ** Warning: [5] ex4.vhd(83): Nonresolved signal 'RES' may have 
multiple sources.
#   Drivers:
#     ex4.vhd(95):Conditional signal assignment line__95
#     ex4.vhd(120):Process line__120
#        Driven at:
#           ex4.vhd(130)
# ** Error: ex4.vhd(88): Nonresolved signal 'mux_o' has multiple 
sources.
#   Drivers:
#     ex4.vhd(106):Statement my_mux
#     ex4.vhd(94):Conditional signal assignment line__94
# ** Error: ex4.vhd(88): Nonresolved signal 'last_RES' has multiple 
sources.
#   Drivers:
#     ex4.vhd(116):Statement RES_DFF
#     ex4.vhd(93):Conditional signal assignment line__93
# ** Warning: [5] ex4.vhd(88): Nonresolved signal 'tran_RES' may have 
multiple sources.
#   Drivers:
#     ex4.vhd(97):Conditional signal assignment line__97
#     ex4.vhd(120):Process line__120
#        Driven at:
#           ex4.vhd(125)
# ** Error: ex4.vhd(89): Nonresolved signal 'sel_mux' has multiple 
sources.
#   Drivers:
#     ex4.vhd(111):Statement MUX_DFF
#     ex4.vhd(96):Conditional signal assignment line__96
# ** Error: ex4.vhd(139): VHDL Compiler exiting
# D:/Modeltech_pe_edu_10.2a/win32pe_edu/vcom failed.



thanks in advance, Amitai

Thanks very much for the quick answer.

I understood the meaning of the clock- it needs to be
controlled from the testbench and not by the component itself.

The problem of the multiple sources I managed to Reduce to one-

# ** Error: checkex4.vhd(103): Nonresolved signal 'cur_RES' has multiple 
sources.

which is the output of the FF whom is responsible for the memory
for the next cycle. I don't see why there is a problem with the code.
(I can guess it's connected to the clock and sync options ?)


Thanks, Amitai