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Forum: FPGA, VHDL & Verilog Can Someone Help Me Write an I2C Controller


von Joe D. (paparit432)


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It should be a an I2C Controller than can perform a single byte write. 
Compensation may be considered

von PittyJ (Guest)


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Tell us, what you already know and have.
How far are you with your current code?
What is the problem in detail?

von Martin (Guest)


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Do you have to write it on your own?
Otherwise have a look at: http://opencores.org/project,i2c

von Lothar M. (lkmiller) (Moderator)


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Joe Daddy wrote:
> It should be a an I2C Controller than can perform a single byte write.
I have one written in Assembler, runing on a NEC uPD78017663A.
Will that be ok?

von Joe D. (paparit432)


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1
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
USE ieee.std_logic_unsigned.all;
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ENTITY i2c_master IS
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  GENERIC(
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    input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
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    bus_clk   : INTEGER := 400_000);   --speed the i2c bus (scl) will run at in Hz
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  PORT(
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    clk       : IN     STD_LOGIC;                    --system clock
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    reset_n   : IN     STD_LOGIC;                    --active low reset
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    ena       : IN     STD_LOGIC;                    --latch in command
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    addr      : IN     STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
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    rw        : IN     STD_LOGIC;                    --'0' is write, '1' is read
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    data_wr   : IN     STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
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    busy      : OUT    STD_LOGIC;                    --indicates transaction in progress
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    data_rd   : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
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    ack_error : BUFFER STD_LOGIC;                    --flag if improper acknowledge from slave
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    sda       : INOUT  STD_LOGIC;                    --serial data output of i2c bus
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    scl       : INOUT  STD_LOGIC);                   --serial clock output of i2c bus
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END i2c_master;
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ARCHITECTURE logic OF i2c_master IS
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  CONSTANT divider  :  INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
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  TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
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  SIGNAL  state     :  machine;                          --state machine
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  SIGNAL  data_clk  :  STD_LOGIC;                        --clock edges for sda
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  SIGNAL  scl_clk   :  STD_LOGIC;                        --constantly running internal scl
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  SIGNAL  scl_ena   :  STD_LOGIC := '0';                 --enables internal scl to output
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  SIGNAL  sda_int   :  STD_LOGIC := '1';                 --internal sda
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  SIGNAL  sda_ena_n :  STD_LOGIC;                        --enables internal sda to output
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  SIGNAL  addr_rw   :  STD_LOGIC_VECTOR(7 DOWNTO 0);     --latched in address and read/write
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  SIGNAL  data_tx   :  STD_LOGIC_VECTOR(7 DOWNTO 0);     --latched in data to write to slave
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  SIGNAL  data_rx   :  STD_LOGIC_VECTOR(7 DOWNTO 0);     --data received from slave
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  SIGNAL  bit_cnt   :  INTEGER RANGE 0 TO 7 := 7;        --tracks bit number in transaction
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  SIGNAL  stretch   :  STD_LOGIC := '0';                 --identifies if slave is stretching scl
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BEGIN
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  --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
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  PROCESS(clk, reset_n)
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    VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
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  BEGIN
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    IF(reset_n = '0') THEN               --reset asserted
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      stretch <= '0';
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      count := 0;
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    ELSIF(clk'EVENT AND clk = '1') THEN
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      IF(count = divider*4-1) THEN       --end of timing cycle
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        count := 0;                      --reset timer
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      ELSIF(stretch = '0') THEN          --clock stretching from slave not detected
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        count := count + 1;              --continue clock generation timing
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      END IF;
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      CASE count IS
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        WHEN 0 TO divider-1 =>           --first 1/4 cycle of clocking
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          scl_clk <= '0';
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          data_clk <= '0';
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        WHEN divider TO divider*2-1 =>   --second 1/4 cycle of clocking
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          scl_clk <= '0';
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          data_clk <= '1';
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        WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
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          scl_clk <= 'Z';                --release scl
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          IF(scl = '0') THEN             --detect if slave is stretching clock
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            stretch <= '1';
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          ELSE
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            stretch <= '0';
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          END IF;
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          data_clk <= '1';
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        WHEN OTHERS =>                   --last 1/4 cycle of clocking
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          scl_clk <= 'Z';
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          data_clk <= '0';
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      END CASE;
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    END IF;
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  END PROCESS;

von Joe D. (paparit432)


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The above code is what I have so far. I know it is incomplete, but I 
need the I2c to perform a single byte write and a single byte read. At 
this point I am confused on where to go from here.

von Duke Scarring (Guest)


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Do you have a testbench?
Without testbench simulation is not possible. Test on hardware Without 
simulation is like Russian roulette...

Duke

von Manni (Guest)


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>Russian roulette...
You mean, we all can die from a bad coding?

I have a question about this subject: Does anybody know about I2C 
patents a license issues? I recently was told I2C was under protection 
and has to b licensed for commercial use.

von Max (Guest)


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Atmel showed how to bypass the License, just call it twi :-)

von Joe D. (paparit432)


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I am willing to compensate anyone who is willing to assist me

von Tom (Guest)


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Do you have a requirement SPEC?
Hourly Rates for such projects are around €60,-

von Fitzebutze (Guest)


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Hi,

I've got an i2c single master-only engine ready, but it kinda requires a 
soft CPU to be useful. Basically it is a module of a System on Chip 
design.

Example access (from the soft CPU core firmware):
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int i2c_write16(unsigned int addr, unsigned int data)
2
{
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  MMR(I2C_Ctrl)      = 1-1; // One byte per transaction
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  MMR(I2C_SlaveAddr) = (addr >> 15) & ~1; // Write address
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  MMR(I2C_WData)     = (addr >> 8) & 0xff;
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  wait_ready();
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  MMR(I2C_WData)     = addr & 0xff;
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  wait_ready();
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  MMR(I2C_WData)     = data >> 8;
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  wait_ready();
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  MMR(I2C_WData)     = data;
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  wait_ready();
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  while ((MMR(I2C_Stat) & INACK)); // wait until stop phase reached
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  if (MMR(I2C_Stat) & NAK) return -1; 
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  return 0;
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}

In order to draft some pecuniary house numbers of the support expenses, 
you might have to post more about the requirements (what HW it should 
support, what soft core you'd be using, etc. )
BTW: No need to worry about any licensing issues, the patent has expired 
a while ago.

Greetings,

Butze

von Joe D. (paparit432)


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To Fitzebutze,

Can you send me an email to paparit432@yahoo.com? I wanna discuss the 
I2C controller further in depth and I also want to send you additional 
documents regarding this as well?

von Joe D. (paparit432)


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Tom wrote:
> Do you have a requirement SPEC?
> Hourly Rates for such projects are around €60,-

Yes.

Send me a personal message @ paparit432@yahoo.com and we can talk 
further.

von fpgaengineer (Guest)


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is this project still open? i could provide you with a working scalable 
iwc controller offering a dynamic number of inputs and outputs 
configurable by genererics, data is stored in brams

it comes complete with testbench and implementation example for both 
xilinx and altera devices

von Joe D. (paparit432)


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fpgaengineer wrote:
> is this project still open? i could provide you with a working scalable
> iwc controller offering a dynamic number of inputs and outputs
> configurable by genererics, data is stored in brams
>
> it comes complete with testbench and implementation example for both
> xilinx and altera devices

Please email me at paparit432@yahoo.com

von Wayne Gretzky (Guest)


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You want to pay for a simple i2C?  For a fex lines of code?
Why not using OS?

von Anush Kompally (Guest)


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Hello there,

Can you tell me why the divider in the code is set to 
"(input_clk/bus_clk)/4".

von anynomous (Guest)


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because it takes various operarion frequencies into account

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