Dear all,
I have some serious issues with the GCC compiler when using a cortex-M0
(STM32F051)
When compiling my code with GCC version 4.6.3, which should support
cortex-M0 microcontrollers, I get next messages:
Error: unknown cpu `cortex-m0'
Error: unrecognized option -mcpu=cortex-m0
When compiling the same code with the codesourcery lite package (same
gcc version), it works fine, however I like to configure my own gcc
version.
I configured GCC with next options:
../configure --target=arm-axon-eabi --prefix=toolchain \
--with-cpu=cortex-m0 --with-mode=thumb \
--enable-interwork --disable-multilib \
--enable-languages="c" --with-newlib --without-headers \
--disable-shared --with-gnu-as --with-gnu-ld \
2>&1 | tee configure.log
Looking in the logging, the cortex-m0 is recognized
Also with the newest version 4.7.2 I have the same problems
Who can help me with this issue?
Regards,
Evert
Hi, I use an Arduino... Maybe it helps, if you write: "-mmcu=", but I'm not sure, just test it... MfG Marces
I use this congfiguration: ../gcc-4.6-4.6.3/gcc-4.6.3/configure --target=arm-none-eabi --enable-interwork --enable-multilib --enable-languages=c,c++ --with-newlib --with-headers=/home/user/gcc-4.6.3/newlib-1.18.0/newlib/libc/include --disable-libssp --disable-nls --with-system-zlib --prefix=/home/user/gcc-4.6.3/gcc-4.6.3-install --with-mpc=/home/user/gcc-4.6.3/gcc-4.6.3-install --with-mpfr=/home/user/gcc-4.6.3/gcc-4.6.3-install --with-gmp=/home/user/gcc-4.6.3/gcc-4.6.3-install and I replaced the file gcc-4.6-4.6.3/gcc-4.6.3/gcc/config/arm/t-arm-elf with the attached file
Hi, Try this cross-compiler: https://launchpad.net/gcc-arm-embedded it is dedicated for various versions of cortex processors. On this page there is a readme link with info about (I use this for cm3 and cm4). MacLyon
Depending on where that Error came from exactly, the issue might be similiar to one I had with AVRs. There avr-gcc would not complain about -mmcu=atmega8 while avr-ld does only accept architecture names, i.e. --mmcu=avr4 .
Evert wrote: > Error: unknown cpu `cortex-m0' Run it as "arm-...-gcc --target-help", and it will tell you which CPU types are recognized. I've got an elderly GCC 4.6.0 around, and it properly supports Cortex-M0 CPUs:
1 | $ arm-none-eabi-gcc --target-help |
2 | The following options are target specific: |
3 | -mabi= Specify an ABI |
4 | -mabort-on-noreturn Generate a call to abort if a noreturn function |
5 | returns |
6 | -mapcs-float Pass FP arguments in FP registers |
7 | -mapcs-frame Generate APCS conformant stack frames |
8 | -mapcs-reentrant Generate re-entrant, PIC code |
9 | -march= Specify the name of the target architecture |
10 | -mbig-endian Assume target CPU is configured as big endian |
11 | -mcallee-super-interworking Thumb: Assume non-static functions may be called |
12 | from ARM code |
13 | -mcaller-super-interworking Thumb: Assume function pointers may go to non- |
14 | Thumb aware code |
15 | -mcirrus-fix-invalid-insns Cirrus: Place NOPs to avoid invalid instruction |
16 | combinations |
17 | -mcpu= Specify the name of the target CPU |
18 | -mfix-cortex-m3-ldrd Avoid overlapping destination and address |
19 | registers on LDRD instructions that may trigger |
20 | Cortex-M3 errata. |
21 | -mfloat-abi= Specify if floating point hardware should be used |
22 | -mfp16-format= Specify the __fp16 floating-point format |
23 | -mfpu= Specify the name of the target floating point |
24 | hardware/format |
25 | -mhard-float Alias for -mfloat-abi=hard |
26 | -mlittle-endian Assume target CPU is configured as little endian |
27 | -mlong-calls Generate call insns as indirect calls, if |
28 | necessary |
29 | -mpic-register= Specify the register to be used for PIC addressing |
30 | -mpoke-function-name Store function names in object code |
31 | -msched-prolog Permit scheduling of a function's prologue |
32 | sequence |
33 | -msingle-pic-base Do not load the PIC register in function prologues |
34 | -msoft-float Alias for -mfloat-abi=soft |
35 | -mstructure-size-boundary= Specify the minimum bit alignment of structures |
36 | -mthumb Compile for the Thumb not the ARM |
37 | -mthumb-interwork Support calls between Thumb and ARM instruction |
38 | sets |
39 | -mtp= Specify how to access the thread pointer |
40 | -mtpcs-frame Thumb: Generate (non-leaf) stack frames even if |
41 | not needed |
42 | -mtpcs-leaf-frame Thumb: Generate (leaf) stack frames even if not |
43 | needed |
44 | -mtune= Tune code for the given processor |
45 | -mvectorize-with-neon-quad Use Neon quad-word (rather than double-word) |
46 | registers for vectorization |
47 | -mword-relocations Only generate absolute relocations on word sized |
48 | values. |
49 | -mwords-little-endian Assume big endian bytes, little endian words |
50 | |
51 | Known ARM CPUs (for use with the -mcpu= and -mtune= options): |
52 | cortex-m0, cortex-m1, cortex-m3, cortex-m4, cortex-r4f, cortex-r4, |
53 | cortex-a15, cortex-a9, cortex-a8, cortex-a5, arm1156t2f-s, arm1156t2-s, |
54 | mpcore, mpcorenovfp, arm1176jzf-s, arm1176jz-s, arm1136jf-s, arm1136j-s, |
55 | arm1026ej-s, arm926ej-s, fa726te, fmp626, fa626te, fa606te, iwmmxt2, iwmmxt, |
56 | xscale, arm1022e, arm1020e, arm10e, arm968e-s, arm966e-s, arm946e-s, arm9e, |
57 | arm1020t, arm10tdmi, ep9312, arm940t, arm922t, arm920t, arm920, arm9tdmi, |
58 | arm9, arm740t, arm720t, arm710t, arm7tdmi-s, arm7tdmi, fa626, fa526, |
59 | strongarm1110, strongarm1100, strongarm110, strongarm, arm810, arm8, |
60 | arm7dmi, arm7dm, arm7m, arm7500fe, arm7500, arm7100, arm710c, arm720, |
61 | arm710, arm700i, arm700, arm70, arm7di, arm7d, arm7, arm620, arm610, arm600, |
62 | arm60, arm6, arm3, arm250, arm2 |
63 | |
64 | Known ARM architectures (for use with the -march= option): |
65 | iwmmxt2, iwmmxt, ep9312, armv7e-m, armv7-m, armv7-r, armv7-a, armv7, |
66 | armv6-m, armv6t2, armv6zk, armv6z, armv6k, armv6j, armv6, armv5te, armv5e, |
67 | armv5t, armv5, armv4t, armv4, armv3m, armv3, armv2a, armv2 |
68 | Assembler options |
69 | ================= |
70 | … |
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