Dear all,
I have some serious issues with the GCC compiler when using a cortex-M0
(STM32F051)
When compiling my code with GCC version 4.6.3, which should support
cortex-M0 microcontrollers, I get next messages:
Error: unknown cpu `cortex-m0'
Error: unrecognized option -mcpu=cortex-m0
When compiling the same code with the codesourcery lite package (same
gcc version), it works fine, however I like to configure my own gcc
version.
I configured GCC with next options:
../configure --target=arm-axon-eabi --prefix=toolchain \
--with-cpu=cortex-m0 --with-mode=thumb \
--enable-interwork --disable-multilib \
--enable-languages="c" --with-newlib --without-headers \
--disable-shared --with-gnu-as --with-gnu-ld \
2>&1 | tee configure.log
Looking in the logging, the cortex-m0 is recognized
Also with the newest version 4.7.2 I have the same problems
Who can help me with this issue?
Regards,
Evert
I use this congfiguration:
../gcc-4.6-4.6.3/gcc-4.6.3/configure --target=arm-none-eabi
--enable-interwork --enable-multilib --enable-languages=c,c++
--with-newlib
--with-headers=/home/user/gcc-4.6.3/newlib-1.18.0/newlib/libc/include
--disable-libssp --disable-nls --with-system-zlib
--prefix=/home/user/gcc-4.6.3/gcc-4.6.3-install
--with-mpc=/home/user/gcc-4.6.3/gcc-4.6.3-install
--with-mpfr=/home/user/gcc-4.6.3/gcc-4.6.3-install
--with-gmp=/home/user/gcc-4.6.3/gcc-4.6.3-install
and I replaced the file gcc-4.6-4.6.3/gcc-4.6.3/gcc/config/arm/t-arm-elf
with the attached file
Hi,
Try this cross-compiler:
https://launchpad.net/gcc-arm-embedded
it is dedicated for various versions of cortex processors. On this page
there is a readme link with info about (I use this for cm3 and cm4).
MacLyon
Depending on where that Error came from exactly, the issue might be
similiar to one I had with AVRs.
There avr-gcc would not complain about -mmcu=atmega8 while avr-ld does
only accept architecture names, i.e. --mmcu=avr4 .
Evert wrote:> Error: unknown cpu `cortex-m0'
Run it as "arm-...-gcc --target-help", and it will tell you which
CPU types are recognized.
I've got an elderly GCC 4.6.0 around, and it properly supports
Cortex-M0 CPUs:
$ arm-none-eabi-gcc --target-help
The following options are target specific:
-mabi= Specify an ABI
-mabort-on-noreturn Generate a call to abort if a noreturn function
returns
-mapcs-float Pass FP arguments in FP registers
-mapcs-frame Generate APCS conformant stack frames
-mapcs-reentrant Generate re-entrant, PIC code
-march= Specify the name of the target architecture
-mbig-endian Assume target CPU is configured as big endian
-mcallee-super-interworking Thumb: Assume non-static functions may be called
from ARM code
-mcaller-super-interworking Thumb: Assume function pointers may go to non-
Thumb aware code
-mcirrus-fix-invalid-insns Cirrus: Place NOPs to avoid invalid instruction
combinations
-mcpu= Specify the name of the target CPU
-mfix-cortex-m3-ldrd Avoid overlapping destination and address
registers on LDRD instructions that may trigger
Cortex-M3 errata.
-mfloat-abi= Specify if floating point hardware should be used
-mfp16-format= Specify the __fp16 floating-point format
-mfpu= Specify the name of the target floating point
hardware/format
-mhard-float Alias for -mfloat-abi=hard
-mlittle-endian Assume target CPU is configured as little endian
-mlong-calls Generate call insns as indirect calls, if
necessary
-mpic-register= Specify the register to be used for PIC addressing
-mpoke-function-name Store function names in object code
-msched-prolog Permit scheduling of a function's prologue
sequence
-msingle-pic-base Do not load the PIC register in function prologues
-msoft-float Alias for -mfloat-abi=soft
-mstructure-size-boundary= Specify the minimum bit alignment of structures
-mthumb Compile for the Thumb not the ARM
-mthumb-interwork Support calls between Thumb and ARM instruction
sets
-mtp= Specify how to access the thread pointer
-mtpcs-frame Thumb: Generate (non-leaf) stack frames even if
not needed
-mtpcs-leaf-frame Thumb: Generate (leaf) stack frames even if not
needed
-mtune= Tune code for the given processor
-mvectorize-with-neon-quad Use Neon quad-word (rather than double-word)
registers for vectorization
-mword-relocations Only generate absolute relocations on word sized
values.
-mwords-little-endian Assume big endian bytes, little endian words
Known ARM CPUs (for use with the -mcpu= and -mtune= options):
cortex-m0, cortex-m1, cortex-m3, cortex-m4, cortex-r4f, cortex-r4,
cortex-a15, cortex-a9, cortex-a8, cortex-a5, arm1156t2f-s, arm1156t2-s,
mpcore, mpcorenovfp, arm1176jzf-s, arm1176jz-s, arm1136jf-s, arm1136j-s,
arm1026ej-s, arm926ej-s, fa726te, fmp626, fa626te, fa606te, iwmmxt2, iwmmxt,
xscale, arm1022e, arm1020e, arm10e, arm968e-s, arm966e-s, arm946e-s, arm9e,
arm1020t, arm10tdmi, ep9312, arm940t, arm922t, arm920t, arm920, arm9tdmi,
arm9, arm740t, arm720t, arm710t, arm7tdmi-s, arm7tdmi, fa626, fa526,
strongarm1110, strongarm1100, strongarm110, strongarm, arm810, arm8,
arm7dmi, arm7dm, arm7m, arm7500fe, arm7500, arm7100, arm710c, arm720,
arm710, arm700i, arm700, arm70, arm7di, arm7d, arm7, arm620, arm610, arm600,
arm60, arm6, arm3, arm250, arm2
Known ARM architectures (for use with the -march= option):
iwmmxt2, iwmmxt, ep9312, armv7e-m, armv7-m, armv7-r, armv7-a, armv7,
armv6-m, armv6t2, armv6zk, armv6z, armv6k, armv6j, armv6, armv5te, armv5e,
armv5t, armv5, armv4t, armv4, armv3m, armv3, armv2a, armv2
Assembler options
=================
…
Watch this topic
Disable multi-page view