Hi,
I am trying to run vhdl code of d flip flop on ghdl.
I am not getting any error while compiling and executing,however when I
try to run it, it doesnt come to prompt again it keeps on runing.
Please let me know where I am making mistake.
My code is as below.
> it keeps on runing.
Which toolchain do you use?
Usually there's also a button "run for a specified time". There you can
say: run my simulation for 100ns, then stop.
BTW:
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dut_dff:dffportmap(T_din,T_dclk,T_qout,T_nqout);
Don't use positional assignment. I promise you: you will run into
problems with this after the first minor change. Where's the problem
here:
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dut_dff:dffportmap(T_din,T_dclk,T_nqout,T_qout);
Write it with explicit assignments, and then you can twist and move
every port:
Fahim Khan wrote:> if (err_cnt=0) then> assert false> report "Testbench of Adder completed successfully!"> severity note;> else> assert true> report "Something wrong, try again"> severity error;> end if;
Wrong, needs to be:
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if(err_cnt=0)then
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assertfalse
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report"Testbench of Adder completed successfully!"
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severityfailure;
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else
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assertfalse
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report"Something wrong, try again"
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severityfailure;
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endif;
The assert condition has always to be "false", if you want it to trig...
...then it will work as expected. And to be sure it stops, use severity
"failure", this is usually a break condition by default.
With GHDL and other simulators (e.g. ModelSim) I usually have in my TB:
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clk_process:process
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begin
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waitforclk_period*5;
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loop
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clk50<='1';
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waitforclk_period/2;
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clk50<='0';
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waitforclk_period/2;
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exitwhenend_of_sim='1';
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endloop;
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wait;
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endprocess;
...this (or something similar) for all special processes I have in the
TB...
And in my 'main' TB execution process (snippet of the end of this
process):
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--assert end_of_sim = '1'
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-- report "---- End of module simulation reached ----" severity note;
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end_of_sim<='1';
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wait;
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endprocess;
This will stop GHDL and others, either with the 'assert' (commented out
here) or 'automagically'... (of course, 'end_of_sim'
initially/previously set to '0')