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Forum: FPGA, VHDL & Verilog Testbench of d flip flop


von Fahim K. (fahimk)


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Hi,

I am trying to run vhdl code of d flip flop on ghdl.

I am not getting any error while compiling and executing,however when I 
try to run it, it doesnt come to prompt again it keeps on runing.
Please let me know where I am making mistake.

My code is as below.
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---------------------------------------------
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library ieee ;
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use ieee.std_logic_1164.all;
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---------------------------------------------
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entity dff is
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port ( din:     in std_logic;
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       dclk:     in std_logic;
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       qout:    out std_logic;
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       nqout:   out std_logic
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     );
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end dff;
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--------------------------------------------
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architecture behavioral of dff is
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begin
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        process(din,dclk)
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        begin
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          --- clock rising edge
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        if(dclk='1' and dclk'event) then
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                qout <= din;
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                nqout <= not din;
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        end if;
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        end process;
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end behavioral;
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------------------------------------------              
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------TestBench of D Flip Flop------------                      
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------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity dff_tb is
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end dff_tb;
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------------------------------------------
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architecture testbench of dff_tb is
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        signal T_din:   std_logic;
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        signal T_dclk:  std_logic;
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        signal T_qout:  std_logic;
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        signal T_nqout: std_logic;
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        constant clk_period : time := 50 ns;
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        component dff
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        port ( din:     in std_logic;
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               dclk:    in std_logic;
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               qout:    out std_logic;
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               nqout:   out std_logic
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             );
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        end component;
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begin
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    dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);
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    process
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        begin
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          T_dclk <= '0';
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          wait for clk_period/2;
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          T_dclk <= '1';
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          wait for clk_period/2;
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    end process;
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    process
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        begin
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          --case1
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          T_din <= '0';
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          wait for clk_period*2;
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          --case2
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          T_din <= '1';
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          wait for clk_period*1.5;
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          --case3
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          T_din <= '0';
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          wait for clk_period*0.5;
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          --case4
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          T_din <= '1';
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        wait;
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   end process;
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end testbench;

von P. K. (pek)


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You have to stop the testbench somehow at the end, e.g. by an assertion 
like:
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    assert false
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      report " ===== Verification run 'TESTBENCH' finished ====="
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      severity failure;

Otherwise, your clock process will run forever...

von Lothar M. (lkmiller) (Moderator)


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> it keeps on runing.
Which toolchain do you use?
Usually there's also a button "run for a specified time". There you can 
say: run my simulation for 100ns, then stop.

BTW:
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     dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);
Don't use positional assignment. I promise you: you will run into 
problems with this after the first minor change. Where's the problem 
here:
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     dut_dff: dff port map (T_din,T_dclk,T_nqout,T_qout);
Write it with explicit assignments, and then you can twist and move 
every port:
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dut_dff: dff port map (qout=>T_qout,din=>T_din,dclk=>T_dclk,nqout=>T_nqout);

von Fahim K. (fahimk)


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Hi,

I changed the code to use assert statement but still getting same issue.
1
---------------------------------------------
2
library ieee ;
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use ieee.std_logic_1164.all;
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---------------------------------------------
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entity dff is
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port ( din:  in std_logic;
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       dclk:     in std_logic;
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       qout:    out std_logic;
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       nqout:   out std_logic
13
     );
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end dff;
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--------------------------------------------
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architecture behavioral of dff is
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begin
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  process(din,dclk)
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  begin
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    --- clock rising edge
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  if(dclk='1' and dclk'event) then
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    qout <= din;
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    nqout <= not din;
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  end if;
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  end process;
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end behavioral;
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------------------------------------------    
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------TestBench of D Flip Flop------------      
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------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity dff_tb is
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end dff_tb;
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------------------------------------------
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architecture testbench of dff_tb is
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  signal T_din:  std_logic;
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  signal T_dclk:  std_logic;
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  signal T_qout:  std_logic;
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  signal T_nqout: std_logic;
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  component dff 
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  port ( din:   in std_logic;
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         dclk:  in std_logic;
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         qout:    out std_logic;
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         nqout:  out std_logic
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       );
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  end component;
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begin
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    dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);
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    process
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  begin
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    T_dclk <= '0';
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    wait for 5 ns;
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    T_dclk <= '1';
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    wait for 5 ns;
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    end process;
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    process 
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  variable err_cnt: integer := 0; 
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  begin
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    --case1
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   T_din <= '1';
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  wait for 12 ns;     
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  assert (T_qout='1') report "Error1!" severity error;
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  if (T_qout/='1') then
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      err_cnt := err_cnt + 1;
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  end if;
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  -- case 2
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  T_din <=  '0';   
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  wait for 28 ns;
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  assert (T_qout='0') report "Error2!" severity error;
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  if (T_qout/='0') then
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      err_cnt := err_cnt + 1;
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  end if;
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  -- case 3
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  T_din <= '1';            
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  wait for 2 ns;
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  assert (T_qout='0') report "Error3!" severity error;
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  if (T_qout/='0') then
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      err_cnt := err_cnt + 1;
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  end if;
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  -- case 4
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  T_din <= '0';
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  wait for 10 ns;
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  assert (T_qout='0') report "Error4!" severity error;
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  if (T_qout/='0') then
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      err_cnt := err_cnt + 1;
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  end if;
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  -- case 5
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  T_din <=  '1';    
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  wait for 20 ns;    
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  assert (T_qout='1') report "Error5!" severity error;   
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  if (T_qout/='0') then
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      err_cnt := err_cnt + 1;
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  end if;
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  -- summary of all the tests
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  if (err_cnt=0) then       
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      assert false 
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      report "Testbench of Adder completed successfully!" 
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      severity note; 
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  else 
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      assert true 
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      report "Something wrong, try again" 
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      severity error; 
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  end if; 
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  wait;
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   end process;
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end testbench;

von Fahim K. (fahimk)


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Hi,

I am using ghdl.

von Fahim K. (fahimk)


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Got it I am stoping it after 500ns using

ghdl -r dff_tb --stop-time=500ns

von P. K. (pek)


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Fahim Khan wrote:
>   if (err_cnt=0) then
>       assert false
>       report "Testbench of Adder completed successfully!"
>       severity note;
>   else
>       assert true
>       report "Something wrong, try again"
>       severity error;
>   end if;

Wrong, needs to be:
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   if (err_cnt=0) then
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       assert false
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       report "Testbench of Adder completed successfully!"
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       severity failure;
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   else
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       assert false
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       report "Something wrong, try again"
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       severity failure;
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   end if;

The assert condition has always to be "false", if you want it to trig...
...then it will work as expected. And to be sure it stops, use severity 
"failure", this is usually a break condition by default.

von berndl (Guest)


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With GHDL and other simulators (e.g. ModelSim) I usually have in my TB:
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   clk_process : process
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   begin
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    wait for clk_period*5;
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    loop
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      clk50 <= '1';
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      wait for clk_period/2;
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      clk50 <= '0';
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      wait for clk_period/2;
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      exit when end_of_sim = '1';
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    end loop;
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    wait;
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   end process;
...this (or something similar) for all special processes I have in the 
TB...

And in my 'main' TB execution process (snippet of the end of this 
process):
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    --assert end_of_sim = '1'
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    --  report "---- End of module simulation reached ----" severity note;
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    end_of_sim <= '1';
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    wait;
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   end process;

This will stop GHDL and others, either with the 'assert' (commented out 
here) or 'automagically'... (of course, 'end_of_sim' 
initially/previously set to '0')

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