Hi, I am trying to run vhdl code of d flip flop on ghdl. I am not getting any error while compiling and executing,however when I try to run it, it doesnt come to prompt again it keeps on runing. Please let me know where I am making mistake. My code is as below.
1 | ---------------------------------------------
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2 | |
3 | library ieee ; |
4 | use ieee.std_logic_1164.all; |
5 | |
6 | |
7 | ---------------------------------------------
|
8 | |
9 | entity dff is |
10 | port ( din: in std_logic; |
11 | dclk: in std_logic; |
12 | qout: out std_logic; |
13 | nqout: out std_logic |
14 | );
|
15 | |
16 | end dff; |
17 | --------------------------------------------
|
18 | |
19 | architecture behavioral of dff is |
20 | |
21 | begin
|
22 | process(din,dclk) |
23 | begin
|
24 | --- clock rising edge
|
25 | if(dclk='1' and dclk'event) then |
26 | qout <= din; |
27 | nqout <= not din; |
28 | end if; |
29 | end process; |
30 | end behavioral; |
31 | |
32 | ------------------------------------------
|
33 | ------TestBench of D Flip Flop------------
|
34 | ------------------------------------------
|
35 | |
36 | library ieee; |
37 | use ieee.std_logic_1164.all; |
38 | |
39 | |
40 | entity dff_tb is |
41 | end dff_tb; |
42 | |
43 | |
44 | ------------------------------------------
|
45 | |
46 | architecture testbench of dff_tb is |
47 | |
48 | signal T_din: std_logic; |
49 | signal T_dclk: std_logic; |
50 | signal T_qout: std_logic; |
51 | signal T_nqout: std_logic; |
52 | |
53 | constant clk_period : time := 50 ns; |
54 | |
55 | component dff |
56 | port ( din: in std_logic; |
57 | dclk: in std_logic; |
58 | qout: out std_logic; |
59 | nqout: out std_logic |
60 | );
|
61 | end component; |
62 | |
63 | begin
|
64 | |
65 | dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout); |
66 | |
67 | process
|
68 | begin
|
69 | T_dclk <= '0'; |
70 | wait for clk_period/2; |
71 | T_dclk <= '1'; |
72 | wait for clk_period/2; |
73 | end process; |
74 | |
75 | process
|
76 | |
77 | begin
|
78 | --case1
|
79 | T_din <= '0'; |
80 | wait for clk_period*2; |
81 | |
82 | --case2
|
83 | T_din <= '1'; |
84 | wait for clk_period*1.5; |
85 | |
86 | --case3
|
87 | T_din <= '0'; |
88 | wait for clk_period*0.5; |
89 | |
90 | --case4
|
91 | T_din <= '1'; |
92 | |
93 | wait; |
94 | end process; |
95 | |
96 | end testbench; |