SJ Oh wrote:
> the code I have is compiled perfectly
I can write don some lines of VHDL tha compile rperfectly well, but the
will do nonsens on the hardware. The debugger for VHDL is the funtional
simulator.
> but for some reason it keeps having the same issues
Which ones?
One question:
How fast is your clock?
1 | elsif CLK'event and CLK = '1' then -- how fast ....
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2 | case traffic_light_controller is
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3 | when GR =>
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4 | if count < sec_5 then
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5 | traffic_light_controller <= GR;
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6 | count <= Count+1; -- ... will count count up?
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7 | else
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8 | traffic_light_controller <= YR;
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9 | count<=X"0"; --count is reset to zero
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10 | end if;
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Is it really 1Hz?
This is not the problem, but for me it is a major mistake:
1 | type traffic_light_controller_type is (GR, RY, RR2, YR, RG, RR1);
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2 | signal traffic_light_controller: traffic_light_controller_type;
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3 | |
4 | |
5 | traffic_light_controller_machine: process (CLK,CLR)
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6 | begin
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7 | if CLR='1' then
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8 | traffic_light_controller <= GR;
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9 | elsif CLK'event and CLK = '1' then
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10 | case traffic_light_controller is
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11 | when GR =>
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12 | |
13 | when YR =>
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14 | |
15 | when RR1 =>
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16 | |
17 | when RG =>
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18 |
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19 | when RY =>
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20 | |
21 | when RR2 =>
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22 | |
23 | when others => -- there are no remaining other states !!!!!!
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24 |
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25 | end case;
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when others is not necessary when all of the possible states are used.
The signal traffic_light_controller has only 6 states and each of them
is explicitly used, so there are no "others" remaining!