Maybe it's because your critical path has the same length in both cases 
(i.e. the additional block doesn't matter). So you have to display not 
only your longest path, but all of them.

Further more you have to consider that the synthesizer is optimizing 
your design. The three (here undescribed, but probably very simple) 
units all fit into one LUT, resulting in the same worst case path. So 
the chance is good that even the other (not yet displayed) paths have 
the same or similar length...

Dileep L. wrote:
> how to calculate the delay in both the cases???
You have nothing to calculate, just read the value: 7,269ns. Thats it.

This consists of 5 values:
pad(in) --- routing --- LUT --- routing --- pad(out)
769ps       828ps       418ps   828ps       4.426ns

> synthesis report shows the same value in both the cases!!!!!!!!!!!!!!
The synthesis report does for sure not show any timings at all.
Timing is generated after place&route. And the timing report shows, 
that the same hardware is generated in both cases.



BTW: pls chek the following keys on your keyboard: ? ! .
They obviously tend to stuck...  :-/