Multi-source

eduardo m. OP #2944702
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Hello.

I am trying to make a mac component. Everything is fine, until I put 
reg_acc (my accumulator) receiving the output value.
The strange thing is that Quartus sythetize it, but Modelsim acuse a 
multi-source and responde with X in output value.
Do you guys have any ideas?

Here is the code:
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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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ENTITY main IS

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generic (

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size : integer := 4;

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port (

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clk : in std_logic;

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rst : in std_logic;

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a_i : in std_logic_vector(size-1 downto 0);

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b_i : in std_logic_vector(size-1 downto 0);

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out_o : out std_logic_vector(2*size-1 downto 0)

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);

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END main;

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ARCHITECTURE bhv OF main IS

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COMPONENT mac

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generic (

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width : integer);

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port (

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clk : in std_logic;

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rst : in std_logic;

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a_i : in std_logic_vector(width-1 downto 0);

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b_i : in std_logic_vector(width-1 downto 0);

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acc : in std_logic_vector(2*width-1 downto 0);

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out_sig : out std_logic_vector(2*width-1 downto 0)

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);

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END COMPONENT;

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signal acc, out_sig, out_acc : std_logic_vector(2*size-1 downto 0) := (others => '0');

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BEGIN

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mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig);

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reg_out : process(clk, rst)

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begin

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if rst = '1' then

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out_o <= (others => '0');

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elsif clk'event and clk = '1' then

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out_o <= out_sig;

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end if;

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end process; 

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reg_acc : process(clk, rst)  ---> HERE IS THE TROUBLE

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begin

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if rst = '1' then

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acc <= (others => '0');

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elsif clk'event and clk = '1' then

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acc <= out_sig;

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end if;

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end process; 

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END bhv;
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guest Guest #2944737
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Hi,

maybe it´s a problem that the two processes reg_out and reg_acc do the 
same, just the names of the signals the values are assigned to are 
different (out_o vs. acc). So maybe the result is ONE net with TWO Names 
and this causes Modelsim to respond with a multi-source error.

But then I don´t know why Quartus synthesizes it (are there warnings?). 
Did you take a look at the synthesized circuit?
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