Hello. I am trying to make a mac component. Everything is fine, until I put reg_acc (my accumulator) receiving the output value. The strange thing is that Quartus sythetize it, but Modelsim acuse a multi-source and responde with X in output value. Do you guys have any ideas? Here is the code:
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | |
5 | |
6 | ENTITY main IS |
7 | generic ( |
8 | size : integer := 4; |
9 | port ( |
10 | clk : in std_logic; |
11 | rst : in std_logic; |
12 | a_i : in std_logic_vector(size-1 downto 0); |
13 | b_i : in std_logic_vector(size-1 downto 0); |
14 | out_o : out std_logic_vector(2*size-1 downto 0) |
15 | );
|
16 | END main; |
17 | |
18 | |
19 | |
20 | |
21 | ARCHITECTURE bhv OF main IS |
22 | COMPONENT mac |
23 | generic ( |
24 | width : integer); |
25 | port ( |
26 | clk : in std_logic; |
27 | rst : in std_logic; |
28 | a_i : in std_logic_vector(width-1 downto 0); |
29 | b_i : in std_logic_vector(width-1 downto 0); |
30 | acc : in std_logic_vector(2*width-1 downto 0); |
31 | out_sig : out std_logic_vector(2*width-1 downto 0) |
32 | );
|
33 | END COMPONENT; |
34 | |
35 | |
36 | signal acc, out_sig, out_acc : std_logic_vector(2*size-1 downto 0) := (others => '0'); |
37 | |
38 | |
39 | BEGIN
|
40 | |
41 | mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig); |
42 | |
43 | |
44 | reg_out : process(clk, rst) |
45 | begin
|
46 | if rst = '1' then |
47 | out_o <= (others => '0'); |
48 | elsif clk'event and clk = '1' then |
49 | out_o <= out_sig; |
50 | end if; |
51 | end process; |
52 | |
53 | |
54 | reg_acc : process(clk, rst) ---> HERE IS THE TROUBLE |
55 | begin
|
56 | if rst = '1' then |
57 | acc <= (others => '0'); |
58 | elsif clk'event and clk = '1' then |
59 | acc <= out_sig; |
60 | end if; |
61 | end process; |
62 | |
63 | |
64 | |
65 | |
66 | END bhv; |