Hello. I am trying to make a mac component. Everything is fine, until I put reg_acc (my accumulator) receiving the output value. The strange thing is that Quartus sythetize it, but Modelsim acuse a multi-source and responde with X in output value. Do you guys have any ideas? Here is the code:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTITY main IS generic ( size : integer := 4; port ( clk : in std_logic; rst : in std_logic; a_i : in std_logic_vector(size-1 downto 0); b_i : in std_logic_vector(size-1 downto 0); out_o : out std_logic_vector(2*size-1 downto 0) ); END main; ARCHITECTURE bhv OF main IS COMPONENT mac generic ( width : integer); port ( clk : in std_logic; rst : in std_logic; a_i : in std_logic_vector(width-1 downto 0); b_i : in std_logic_vector(width-1 downto 0); acc : in std_logic_vector(2*width-1 downto 0); out_sig : out std_logic_vector(2*width-1 downto 0) ); END COMPONENT; signal acc, out_sig, out_acc : std_logic_vector(2*size-1 downto 0) := (others => '0'); BEGIN mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig); reg_out : process(clk, rst) begin if rst = '1' then out_o <= (others => '0'); elsif clk'event and clk = '1' then out_o <= out_sig; end if; end process; reg_acc : process(clk, rst) ---> HERE IS THE TROUBLE begin if rst = '1' then acc <= (others => '0'); elsif clk'event and clk = '1' then acc <= out_sig; end if; end process; END bhv;
Hi, maybe it´s a problem that the two processes reg_out and reg_acc do the same, just the names of the signals the values are assigned to are different (out_o vs. acc). So maybe the result is ONE net with TWO Names and this causes Modelsim to respond with a multi-source error. But then I don´t know why Quartus synthesizes it (are there warnings?). Did you take a look at the synthesized circuit?
I attached a screenshot of quartus ciruit.
What does the testbench look like? And which signal goes X? Is there an assignment on the output signal?
Take a look.
You assign "out_sig" to "out_o". Check, whether "out_sig" is properly assigned a value to (within "mac"), as there are X'es from the start of the simulation...
There is another Eduardo, he got this recommendation: from: http://embdev.net/topic/279214#2943300 >3) Don't use positional assignments. Use the named assignment! Makes you >code much more readable. Just follow this advice, then you will see your mistake.. Startpoint: mac1: mac GENERIC MAP (width => size) PORT MAP (clk => clk, rst => rst, a_i => a_i, ....
Thanks for the answers!