1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 | use ieee.numeric_std.all;
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6 |
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7 | ENTITY main IS
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8 | generic (
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9 | size : integer := 4);
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10 | port (
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11 | clk : in std_logic;
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12 | rst : in std_logic;
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13 | a_i : in std_logic_vector(size-1 downto 0);
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14 | b_i : in std_logic_vector(size-1 downto 0);
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15 | out_o : out std_logic_vector(2*size-1 downto 0)
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16 | );
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17 | END main;
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18 |
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19 |
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20 | ARCHITECTURE bhv OF main IS
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21 | COMPONENT mac
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22 | generic (
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23 | width : integer);
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24 | port (
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25 | clk : in std_logic;
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26 | rst : in std_logic;
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27 | a_i : in std_logic_vector(width-1 downto 0);
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28 | b_i : in std_logic_vector(width-1 downto 0);
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29 | acc : in std_logic_vector(2*width-1 downto 0);
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30 | out_o : out std_logic_vector(2*width-1 downto 0)
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31 | );
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32 | END COMPONENT;
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33 |
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34 | signal acc : std_logic_vector(2*size-1 downto 0) := (others => '0');
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35 |
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36 |
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37 | BEGIN
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38 |
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39 | mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_o);
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40 |
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41 | END bhv;
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42 |
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43 | library ieee;
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44 | use ieee.std_logic_1164.all;
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45 | use ieee.std_logic_arith.all;
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46 | use ieee.std_logic_unsigned.all;
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47 | use ieee.numeric_std.all;
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48 |
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49 | ENTITY mac IS
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50 | generic (
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51 | width : integer);
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52 | port (
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53 | clk : in std_logic;
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54 | rst : in std_logic;
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55 | a_i : in std_logic_vector(width-1 downto 0);
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56 | b_i : in std_logic_vector(width-1 downto 0);
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57 | acc : in std_logic_vector(2*width-1 downto 0);
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58 | out_o : out std_logic_vector(2*width-1 downto 0)
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59 | );
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60 | END mac;
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61 |
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62 |
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63 | ARCHITECTURE bhv OF mac IS
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64 | COMPONENT mul
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65 | generic (
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66 | W_g : integer);
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67 | port (
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68 | clk : in std_logic;
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69 | rst : in std_logic;
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70 | a_i : in std_logic_vector(W_g-1 downto 0);
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71 | b_i : in std_logic_vector(W_g-1 downto 0);
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72 | outm_o : out std_logic_vector(2*W_g-1 downto 0)
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73 | );
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74 | END COMPONENT;
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75 |
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76 | COMPONENT soma
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77 | generic (
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78 | W_gs : integer);
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79 | port (
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80 | clk : in std_logic;
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81 | rst : in std_logic;
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82 | outm_o : in std_logic_vector(2*W_gs-1 downto 0);
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83 | acc : in std_logic_vector(2*W_gs-1 downto 0);
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84 | outs_o : out std_logic_vector(2*W_gs-1 downto 0)
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85 | );
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86 | END COMPONENT;
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87 |
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88 | signal outm_o, outs_o : std_logic_vector (2*width-1 downto 0) := (OTHERS => '0');
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89 |
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90 |
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91 | BEGIN
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92 | mul1: mul GENERIC MAP (width) PORT MAP (clk, rst, a_i, b_i, outm_o);
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93 | soma1: soma GENERIC MAP (width) PORT MAP (clk, rst, outm_o, acc, outs_o);
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94 | out_o <= outs_o;
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95 | END bhv;
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