I'm trying to write a behavioural description of an 8-bit binary
counter. my code is as follows. I keep getting an error that says:
near text "process"; expecting "if";
the error is on the line that says "end process;". I thought I might not
have ended one of my if statements but as far as I can tell I have an
"end if;" for each one of my if statements. just wondering what else I
might have done wrong. thanks in advance.
Tom Turner
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT8 is
port(
CLK : in std_logic;
CLR : in std_logic;
DIR : in std_logic;
ENA : in std_logic;
LOAD : in std_logic;
DATA : in std_logic_vector(7 downto 0);
COUNT : out std_logic_vector(7 downto 0)
);
end COUNT8;
architecture behavior of COUNT8 is
begin
process(CLK)
begin
if (CLR = '0') then
COUNT <= "00000000";
else if (CLK'EVENT AND CLK = '1') then
if (LOAD = '0') then
if ENA = '1' then
if DIR = '1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
else
COUNT <= DATA;
end if;
end if;
end process;
end behavior;
U need to add a
1 | end if; |
just before
1 | end process; |
But after setting this right the compiler throwing errors
1 | Error (10309): VHDL Interface Declaration error in COUNT8.vhd(29): interface object "COUNT" of mode out cannot be read. Change object mode to buffer or inout. |
2 | Error (10327): VHDL error at COUNT8.vhd(29): can't determine definition of operator ""+"" -- found 0 possible definitions |
With proper formatting your code looks like this:
1 | process(CLK) begin |
2 | if (CLR = '0') then |
3 | COUNT <= "00000000"; |
4 | else
|
5 | if (CLK'EVENT AND CLK = '1') then |
6 | if (LOAD = '0') then |
7 | if ENA = '1' then |
8 | if DIR = '1' then |
9 | COUNT <= COUNT + 1; |
10 | else
|
11 | COUNT <= COUNT - 1; |
12 | end if; |
13 | end if; |
14 | else
|
15 | COUNT <= DATA; |
16 | end if; |
17 | end if; |
18 | ???????
|
19 | end process; |
What you wanted was this:
1 | process(CLK) begin |
2 | if (CLR = '0') then |
3 | COUNT <= "00000000"; |
4 | elsif (CLK'EVENT AND CLK = '1') then -- an "elsif" is somehow different than an "else if" |
5 | if (LOAD = '0') then |
6 | if ENA = '1' then |
7 | if DIR = '1' then |
8 | COUNT <= COUNT + 1; |
9 | else
|
10 | COUNT <= COUNT - 1; |
11 | end if; |
12 | end if; |
13 | else
|
14 | COUNT <= DATA; |
15 | end if; |
16 | end if; |
17 | end process; |
> But after setting this right the compiler throwing errors 1. You cannot read an output. Use internal signals instead. 2. You cannot add two std_logic vectors with numeric_std. Use unsigned or signed vectors instead. Cast between std_logic_vector and unsigned/singed. See the picture there: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std
thanks this was very helpful. I have changed a few things including using a buffer for my count vector.
Its good to know that your problem has been solved. I have a presentation in next 2 days about VHDL in my university and i am collecting some sample project to show in my presentation and your 8-bit counter seems a good idea. I wonder to know can your post your corrected version of your codes so i can use them in my presentation? tnx
Thomas Turner wrote: > thanks this was very helpful. De nada. > I have changed a few things including using a buffer for my count vector. You did not read my post? It is bad idea to be lazy and NOT to use internal signals. You will find this out sooner or later. The major problem is that a counter signal is not a buffer but a simple internal signal. That was the reason why i wrote: >> Use internal signals instead. I did with full intention not write "use a buffer". Get accustomed to the flowery and talky style of VHDL.
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.