Hi!
simple question
can I use this kind of syntax into verilog :

 case(Fetched[24:4])
                21'bzzzzzzzzzzzzzzzzzzzz0 :nextstate <= ADD;
                21'bzzzzzzzzzzzzzzzzz0zz1 :nextstate <= ADD;
                21'b000zzzzzzzzzzzzzz1001 :nextstate <= MUL; //mult
                21'b01zzzzzzzzzzzzzzz1001 :nextstate <= MUL;
                21'b10z00zzzzzzzz00001001 :nextstate <= MUL;
                21'b10z00zzzzzzzz00001001 :nextstate <= SDS;
                21'b100101111111111110001 :nextstate <= BAE;
                  default: nextstate <= UNKNOW; //should not happens
              endcase

I have no error while simulating but have strange result
(I'm student working on sim vision)

thanks all :)

ok srry
I have to use casez

http://eesun.free.fr/DOC/VERILOG/verilog_manual1.html

Two mistakes:

1. 'z' is not don't care.  Use 'x'
2. Use "casex" instead of "case"

thanx
I'll do that, but why casez is not ok here ?

'z' ist not don't care, it stands for high impedance, a clearly defined 
state, at least for the simulator.

Marcus Harnisch wrote:
> It is actually casez that is preferable here. Specifically for this
> reason Verilog defines '?' as synonym for 'z'. With casex you wouldn't
> be able to distinguish unknowns and dont-cares since both use the same
> symbol.

You are right, see IEEE Std 1364-2001 Chapter 9.5.1
To make the intent more vissible i suggest using casez with '?'.

(Sometimes i have to ask what standard writer are smoking)