Guest
#2907697
Hi! simple question can I use this kind of syntax into verilog :
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I have no error while simulating but have strange result (I'm student working on sim vision) thanks all :)
Guest
#2907706
ok srry I have to use casez http://eesun.free.fr/DOC/VERILOG/verilog_manual1.html
Guest
#2907711
Two mistakes: 1. 'z' is not don't care. Use 'x' 2. Use "casex" instead of "case"
Guest
#2907925
thanx I'll do that, but why casez is not ok here ?
Guest
#2907962
'z' ist not don't care, it stands for high impedance, a clearly defined state, at least for the simulator.
Lattice User wrote: > 'z' ist not don't care, it stands for high impedance, a clearly defined > state, at least for the simulator. It is actually casez that is preferable here. Specifically for this reason Verilog defines '?' as synonym for 'z'. With casex you wouldn't be able to distinguish unknowns and dont-cares since both use the same symbol. Kind regards Marcus
Guest
#2909882
Marcus Harnisch wrote: > It is actually casez that is preferable here. Specifically for this > reason Verilog defines '?' as synonym for 'z'. With casex you wouldn't > be able to distinguish unknowns and dont-cares since both use the same > symbol. You are right, see IEEE Std 1364-2001 Chapter 9.5.1 To make the intent more vissible i suggest using casez with '?'. (Sometimes i have to ask what standard writer are smoking)
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