this is the module that i wrote, but it is not working:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TRQ is
port(
clk: in std_logic; --8.33MHz
clk_gen: in std_logic; --50MHz
rst: in std_logic;
serial_data: in std_logic;
busy: in std_logic;
sclk: out std_logic; --clk for the A/D
convst: out std_logic; --starting the conversion
parallel_data_out: out std_logic_vector(11 downto 0):="000000000000"
);
end TRQ;
architecture ARC_TRQ of TRQ is
signal data_save: std_logic_vector(10 downto 0) :="00000000000";
--save the data to get out synchronous
signal temp_sig: std_logic_vector(4 downto 0); --save the first 4 bits
of data
signal cnt_data: integer range 0 to 15 :=0; --counter of the data bits
signal state: integer range 0 to 2 :=0; --conversion states: 2- delay
before next conversion 1-convert , 0- reading data bits
signal busy_delay: integer range 0 to 67 :=0; --delay until busy
rising edge
signal delay_state: integer range 0 to 4 :=0; --delay 400ns before the
next conversion
signal clk_cnt: integer range 0 to 5 :=0; --counter for sclk generator
signal sclk_en: std_logic :='0'; --enable sclk
signal sclk_sig: std_logic :='0'; --signal for sclk generator
begin
process(clk,rst)
begin
if rst='0' then
convst <= '1';
parallel_data_out <="000000000000";
data_save <= "00000000000";
cnt_data <= 0;
state <= 0;
elsif rising_edge(clk) then
case state is
when 0 => -- conversion state
sclk_en <= '0';
if busy='0' then
convst <= '0';
if busy_delay = 67 then
busy_delay <= 0;
state <= 1;
elsif busy_delay = 1 then --
??????????????????????????????????
convst <= '1'; --
else
busy_delay <= busy_delay+1;
end if;
else
state <= 0;
end if;
when 1 => -- reading data bits state
if busy = '0' then
sclk_en <= '1';
case cnt_data is
when 0 =>
temp_sig(0) <= serial_data;
cnt_data <= cnt_data+1;
when 1 =>
temp_sig(1) <= serial_data;
cnt_data <= cnt_data+1;
when 2 =>
temp_sig(2) <= serial_data;
cnt_data <= cnt_data+1;
when 3 =>
temp_sig(3) <= serial_data;
cnt_data <= cnt_data+1;
when 4 =>
data_save(0) <= serial_data;
cnt_data <= cnt_data+1;
when 5 =>
data_save(1) <= serial_data;
cnt_data <= cnt_data+1;
when 6 =>
data_save(2) <= serial_data;
cnt_data <= cnt_data+1;
when 7 =>
data_save(3) <= serial_data;
cnt_data <= cnt_data+1;
when 8 =>
data_save(4) <= serial_data;
cnt_data <= cnt_data+1;
when 9 =>
data_save(5) <= serial_data;
cnt_data <= cnt_data+1;
when 10 =>
data_save(6) <= serial_data;
cnt_data <= cnt_data+1;
when 11 =>
data_save(7) <= serial_data;
cnt_data <= cnt_data+1;
when 12 =>
data_save(8) <= serial_data;
cnt_data <= cnt_data+1;
when 13 =>
data_save(9) <= serial_data;
cnt_data <= cnt_data+1;
when 14 =>
data_save(10) <= serial_data;
cnt_data <= cnt_data+1;
when 15=>
parallel_data_out <= serial_data & data_save(10 downto 0);
cnt_data <= 0;
state <= 2;
end case;
else
state <= 1;
end if;
when 2 => -- waiting 400ns before next conversion
sclk_en <= '0';
if delay_state = 4 then ----------
state <= 0;
delay_state <= 0;
else
delay_state <= delay_state+1;
end if;
end case;
end if;
end process;
process (rst,clk_gen)
begin
if rst='0' then
sclk_sig <= '0';
clk_cnt <= 0;
elsif rising_edge(clk_gen) then
case clk_cnt is
when 0 =>
sclk_sig <= '0';
clk_cnt <= clk_cnt+1;
when 3 =>
sclk_sig <= '1';
clk_cnt <= clk_cnt+1;
when 5 =>
sclk_sig <= sclk_sig;
clk_cnt <= 0;
when others =>
sclk_sig <= sclk_sig;
clk_cnt <= clk_cnt+1;
end case;
end if;
end process;
sclk <= sclk_sig when sclk_en = '1' else '0';
end ARC_TRQ;
may i have mistakes??
and Peter K. i did not understand you..