Brian Sutin wrote:
> I am modifying some existing VHDL and find the code curious. A snippet
> is attached with two processes. In this snippet, A and B are completely
> independent from C and D. First, is there any reason why the two
> processes could not be combined into one process?
It may be in two processes, because the two things are
independent...
> Second, does the test for sysclk'event do anything?
It tells the synthesizer to generate a flipflop.
> I would think that having sysclk on the process sensitivity list would
> have already enforced the process to run on an event.
The sensitivity list is only for the simulation. It tells the
simulator when it has to recalculate the process.
So, when you write this
1 | process (sysclk) is
|
2 | begin
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3 | if (sysclk'event and sysclk='1') then
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4 | A <= B;
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5 | end if;
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6 | process;
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and this
1 | process (someothersignal) is
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2 | begin
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3 | if (sysclk'event and sysclk='1') then
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4 | A <= B;
|
5 | end if;
|
6 | process;
|
you will get exactly the same hardware, but in the second case the
simulation will be total nuts...
And this here
1 | process (sysclk) is
|
2 | begin
|
3 | if (sysclk'event and sysclk='1') then
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4 | A <= B;
|
5 | end if;
|
6 | process;
|
will look exactly the same like this
1 | process (sysclk) is
|
2 | begin
|
3 | if (sysclk='1') then
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4 | A <= B;
|
5 | end if;
|
6 | process;
|
in simulation, but it will lead to a totally different hardware!
And why? It is because in the second case the sensitivity list is
missing the signal B, because when sysclk ist '1' then every change on
B must be transferred to A immediately.
To keep it short: the sensitivity list is only of interest, if you want
a correctly working simulation. The synthesizer does not use the
sensitivity list at all!
In the best case synthesis informs you that there may be a misalignment
between simulation and reality due to an incomplete sensitivity list.