I am using actel FPGA and 12bit parallel adc adc12010 from ti. As a
beginner I want to write a code for following-
"I will give a ramp voltage of 0-2V to ADC. crystal clock is 50MHz, I am
converting it to 100KHz for ADC. I want FPGA to generate pules till ramp
is less than 1. as ramp reaches 1 no pulses should be produced. For
this I have written following code. (d0 - d11 are I/O pins of FPGA
conected at ADC input.) ADC is always enable. I am storing adc output in
a 12bit variable store.
During synthesis I get the warning which says incomplete sensitivity
list and input ports(d0,d1..) are unused. Also after place & route it is
not showing d0,d1.. as I/O ports (so as to assign the actual pin nos
coresponding to FPGA) . Kindly help me
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
entity adc is
port ( clk,d0,d1: in std_logic ;
d2, d3: in std_logic ;
d5, d6: in std_logic ;
d7, d8: in std_logic ;
d9: in std_logic ;
d10: in std_logic ;
d11: in std_logic ;
d4:in std_logic ;
adc_clk, pulse :out std_logic );
end adc;
architecture behav of adc is
signal count1 : integer range 0 to 500:=1 ;
signal clk1 : std_logic ;
signal O : std_logic ;
begin
process(clk)
begin
if rising_edge(clk) then -- start for 100khz clk1 for adc
if (count1<250) then
clk1 <= '1';
count1<= count1+1;
elsif (count1>=250 and count1<500) then
clk1<='0';
count1 <= count1+ 1;
elsif (count1=500) then
clk1<='1';
count1<=1;
end if;
end if;
end process; -- end process for 100khz clk1
process (clk1)
variable store: std_logic_vector(11 downto 0);
begin
store(0) := d0;
store(1) := d1;
store(2) := d2;
store(3) := d3;
store(4) := d4;
store(5) := d5;
store(6) := d6;
store(7) := d7;
store(8) := d8;
store(9) := d9;
store(10) := d10;
store(11) := d11;
if (clk1 = '1' and clk1'event) then
if (store(11 downto 0) < "010011011001" and store(11 downto
0)> "100000000000") then
O <= clk1;
else
O <= '0';
end if;
end if;
end process;
adc_clk <= clk1;
pulse <= O;
end behav;
Keep your library list compact. Don't use the obsolete synopsys packages!
use IEEE.std_logic_1164.all; --use IEEE.std_logic_unsigned.all; --use IEEE.std_logic_arith.all; use IEEE.NUMERIC_STD.ALL; |
And can you post your testbench? A simulation can show most of design errors. Duke
this cannot be true with std_logic_vector or ? >if (store(11 downto 0) < "010011011001" > and store(11 downto 0)> "100000000000") then
I assume it should be an or... Additionally the way shown is not a good way to generate a "new" clock. Indeed its a very, very poor way. Usually a beginner VHDL design should have exactly 1 clock. Derived timings are done by clock enables...
Attached files:
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parallel_adc.jpg
146 KB, 716 downloads
i attached a simulation output snap! how you give 12-bit input value! If the input is voltage means how you convert voltage into 12-bit digital value!!
Why do you hijack someone others over 2 years old thread? Create a new one for a new question!
@Mr Miller: Why do you not simple moove his question to a new thread, since you are a moderator?
signal count1: STD_LOGIC_VECTOR(9 downto 0); signal clk1 : std_logic; ... ... ... ... if(conv_integer(coun1)<250) then ... ... elseif(conv_integer(coun1)<500) then ... ... elseif(conv_integer(coun1)=500) then ... ... ... count1 <="111111111111"
Lothar M. wrote: > Why do you hijack someone others over 2 years old thread? No more comment... roy wrote: > can i get a vhdl code for ad7608 interfacing How much do you pay? If it is for homework lets try it the ohter way: you start with something, you show it and you report the problems you encountered and we try to help you. But if you do so: start a new thread for your new problem...
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