4 bit adder in ghdl

Fahim K. OP #2845590
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Hi,
I am trying to run the below example with error like
adder.vhdl:30:21: no function declarations for operator "+"
ghdl: compilation error

I am not able to recognise this error.
Can you please let me know where I am making mistake?

Also if the problem is with library then I have uncommented it and got 
different error like.

adder.vhdl:6:10: primary unit "std_logic_arith" not found in library 
"ieee"
adder.vhdl:7:10: primary unit "std_logic_unsigned" not found in library 
"ieee"



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------Adder-------------------------------------------

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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--use ieee.std_logic_arith.all;

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--use ieee.std_logic_unsigned.all;

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-------------------------------------------------------

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entity ADDER IS

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generic( n: natural:=4);

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port (A: in std_logic_vector(n-1 downto 0);

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      B: in std_logic_vector(n-1 downto 0);

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      CARRY: out std_logic;

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      SUM: out std_logic_vector(n-1 downto 0)  

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  );

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end ADDER;

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------------------------------------------------------

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architecture behaviour of ADDER is

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signal result:std_logic_vector(n downto 0);

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begin

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  --result <= ('0' & A)+('0' & B);

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        result <= A + B;

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  SUM <= result(n-1 downto 0);

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  CARRY <= result(n);

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end behaviour;

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---------------------------------------------------------

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---------TestBench--------------------------------------

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---------------------------------------------------------

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library ieee;

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use ieee.std_logic_1164.all;

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--use ieee.std_logic_unsigned.all;

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--use ieee.std_logic_arith.all;

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----------------------------------------------------------

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entity ADDER_TB is        -- entity declaration

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end ADDER_TB;

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---------------------------------------------------------

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architecture struct of ADDER_TB is 

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component ADDER is

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    port(  A:  in std_logic_vector(3 downto 0);

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    B:  in std_logic_vector(3 downto 0);   

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    CARRY:  out std_logic;          

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    SUM:  out std_logic_vector(3 downto 0)

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    );

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    end component;

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    signal A, B:  std_logic_vector(3 downto 0):="0000";

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    signal CARRY:  std_logic;

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    signal SUM:    std_logic_vector(3 downto 0):="0000";

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begin

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  result : ADDER port map(A => A,B => B,CARRY => CARRY,SUM => SUM);

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   process

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     begin

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  --case1

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  A<="0000";

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  B<="0000";

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  wait for 5 ns;

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  ---case2

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  A<="0000";

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  B<="0010";

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  wait for 5 ns;

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  ---case3

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  A<="0010";

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  B<="0100";

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  wait for 5 ns;

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  ----case4

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  A<="0110";

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  B<="1001";

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  wait for 5 ns;

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  ----case5

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  A<="1101";

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  B<="0111";

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  wait;

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   end process;

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end struct;


Regards,
Fahim
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Lothar M. Moderator (Company: Titel) #2845593
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You cannot add two std_logic_vectors with the numeric_std!

You must add two unsigned values (defined in numeric_std) and therefore 
some casts are necessary:
1
signal result: unsigned(n downto 0);

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   result <= unsigned(A) + unsigned(B);

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   SUM    <= std_logic_vector(result(n-1 downto 0));



BTW:
You could add two vectors with std_logic_unsigned and std_logic_arith, 
but its strongly not recommended to use those old synopsys libs!
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Fahim K. OP #2845687
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With -fexplicit  it is giving me same error however with --ieee=synopsys 
i am getting error but different one.

adder.vhdl:28:18: no declaration for "unsigned"
ghdl: compilation error

So I remove the unsigned part and run it with --ieee=synopsys and it 
works for me.

Thanks!!!!!!!!!!
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