Hi, I am trying to run the below example with error like adder.vhdl:30:21: no function declarations for operator "+" ghdl: compilation error I am not able to recognise this error. Can you please let me know where I am making mistake? Also if the problem is with library then I have uncommented it and got different error like. adder.vhdl:6:10: primary unit "std_logic_arith" not found in library "ieee" adder.vhdl:7:10: primary unit "std_logic_unsigned" not found in library "ieee"

------Adder------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; ------------------------------------------------------- entity ADDER IS generic( n: natural:=4); port (A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); CARRY: out std_logic; SUM: out std_logic_vector(n-1 downto 0) ); end ADDER; ------------------------------------------------------ architecture behaviour of ADDER is signal result:std_logic_vector(n downto 0); begin --result <= ('0' & A)+('0' & B); result <= A + B; SUM <= result(n-1 downto 0); CARRY <= result(n); end behaviour; --------------------------------------------------------- ---------TestBench-------------------------------------- --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_unsigned.all; --use ieee.std_logic_arith.all; ---------------------------------------------------------- entity ADDER_TB is -- entity declaration end ADDER_TB; --------------------------------------------------------- architecture struct of ADDER_TB is component ADDER is port( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); CARRY: out std_logic; SUM: out std_logic_vector(3 downto 0) ); end component; signal A, B: std_logic_vector(3 downto 0):="0000"; signal CARRY: std_logic; signal SUM: std_logic_vector(3 downto 0):="0000"; begin result : ADDER port map(A => A,B => B,CARRY => CARRY,SUM => SUM); process begin --case1 A<="0000"; B<="0000"; wait for 5 ns; ---case2 A<="0000"; B<="0010"; wait for 5 ns; ---case3 A<="0010"; B<="0100"; wait for 5 ns; ----case4 A<="0110"; B<="1001"; wait for 5 ns; ----case5 A<="1101"; B<="0111"; wait; end process; end struct; |

Regards, Fahim

You cannot add two std_logic_vectors with the numeric_std! You must add two unsigned values (defined in numeric_std) and therefore some casts are necessary:

signal result: unsigned(n downto 0); result <= unsigned(A) + unsigned(B); SUM <= std_logic_vector(result(n-1 downto 0)); |

BTW: Youcouldadd two vectors with std_logic_unsigned and std_logic_arith, but its stronglynot recommendedto use those old synopsys libs!

Thanks Miller. Just one question if I have to use unsigned then it is neccessary to use ieee.std_logic_unsigned.all; correct? But when I am doing so I am getting the below error. adder.vhdl:6:10: primary unit "std_logic_unsigned" not found in library "ieee" Regards Fahim

try the cmd-line statement '--ieee=synopsys' and probably '-fexplicit' for ghdl...

With -fexplicit it is giving me same error however with --ieee=synopsys i am getting error but different one. adder.vhdl:28:18: no declaration for "unsigned" ghdl: compilation error So I remove the unsigned part and run it with --ieee=synopsys and it works for me. Thanks!!!!!!!!!!

Fahim Khan wrote: > Just one question if I have to use unsigned then it is neccessary to use > ieee.std_logic_unsigned.all; correct? You should NOT use ieee.std_logic_unsigned.all at all! The datatypesunsigendand alsosignedare already defined in numeric_std.