Hi there I have synthesized the same code targeting both Virtex5 and Virtex6. I was expecting to get same number of LUTs because both of them have 6 input LUTs. However number of LUTs for the case of Virtex5 was less than that of Virtex6 by approximately 30 LUTs. Is there any justification for this? Thanks
Osama Al-Khaleel wrote: > However number of LUTs for the case of Virtex5 was less than > that of Virtex6 by approximately 30 LUTs. Compared to a total sum of how many LUTs? 50 or 5000? The amount of logic is only half of the story. A different FPGA has different routing ressources and different routing strategies. And maybe the logic uses less slices and the routing uses more slices. But also the Translate and the P&R algorithms are different....
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