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Hi, I'm very new to VHDL, so sorry in advance for my ignorant questions. I would like to extract 8 bits from a couple of vectors. In the first case, the vector is 128bits and is accessed as if it were 16 bytes. The second vector is some large number of bits, and the byte to be extracted is not bytealigned. Here's the code I've tried:
byteData : buffer std_logic_vector(15 downto 0); constant bitData : std_logic_vector(518 downto 0); variable tempByte : std_logic_vector(7 downto 0); tempByte := byteData((byteIndex * 8 + 7) downto (byteIndex * 8)) xor bitData((bitIndex+7) downto bitIndex);  bitIndex and byteIndex as std_logic_vectors too 
Quartus doesn't like my use of the '*' operator. What is the best way to do this kind of thing? Am I able to indirectly access the bits at certain offsets in the vectors? Should I be using shifts (e.g. sll) instead? Thanks for any insight you can provide. Cheers, Dave
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Usually its a good idea to tell the exact error message... What libraries do you use? As a hint: most probably you have a problem with types. 1. A array index MUST be a integer 2. You cannot simply multiply a vector with an integer
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Hi Lothar, Thanks for the reply. Yes, there is a problem with types. Ok, so after converting to integers, it compiles, thanks. Is there a better/more concise way to access an 8 bit vector within a longer std_logic_vector than the following?
tempByte_from_byte_aligned := byteData((to_integer(unsigned(byteIndex)) * 8 + 7) downto (to_integer(unsigned(byteIndex)) * 8)); tempByte_from_bit_aligned = bitData((to_integer(unsigned(bitIndex))+7) downto to_integer(unsigned(bitIndex))); 
This is the info related to your reply, though not relevant anymore. The errors for the line beginning "tempData :=" are:
Error (10327): VHDL error at ...: can't determine definition of operator ""*""  found 0 possible definitions Error (10327): VHDL error at ...: can't determine definition of operator ""+""  found 0 possible definitions Error (10476): VHDL error at ...: type of identifier "bitIndex" does not agree with its usage as "natural" type 
My libraries are:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; 
Cheers, Dave
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First: kick off the std_logic_unsigned. Because together with the recommended numeric_std you can get double and ambiguous definitions for some operations... Second: don't calculate with unconstrained vectors! Use unsigned signals instead of std_logic vectors! (and of course: with the numeric_std you cannot do calculations with vectors! You must cast the vector to signed or unsigned before calculations)
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> Second: don't calculate with unconstrained vectors! Why not? The few examples I've seen do it frequently. Are bitwise operations ok with vectors? > Use unsigned signals instead of std_logic vectors! > (and of course: with the numeric_std you cannot do calculations with > vectors! You must cast the vector to signed or unsigned before > calculations) I did that and it compiles. I now have my entity's port input/output as std_logic and std_logic_vector, my variables and signals as unsigned (except my bitData array which is a constant std_logic_vector)... is this all ok? Thanks again for your time :)
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David Atol wrote: >> Second: don't calculate with unconstrained vectors! > Why not? The few examples I've seen do it frequently. Get a book from P. Ashenden (they're good) and you won't see std_logic_arith in there. Just a little test: what number is "1001"? Is it 9? Or is it 7? What number is unsigned "1001"? It is 9! And most problematic is the multiplication: a signed mult is much different than a unsigned mult. And so, all in all: don't do calculations with unconstrained vectors. Even if you can find it in a lot of books from the last millennium... > Are bitwise operations ok with vectors? Of course they are...
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Lothar Miller wrote: > Get a book from P. Ashenden (they're good) and you won't see > std_logic_arith in there. Ok I got one from last decade based on the one from last millennium... ;p >> Are bitwise operations ok with vectors? > Of course they are... As I thought. It makes sense that it should be fine for add/subtract/rotate/logicalshift but not mult/div/arithmeticshift due to how the sign is handled. Ok, thanks very much for your help.
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> As I thought. It makes sense that it should be fine for > add/subtract/rotate/logicalshift but not mult/div/arithmeticshift due > to how the sign is handled. drop add/subtract and others from your list, too! This should be handled with the numeric_std librarytypes signed and unsigned. std_logic_vector is just a bunch of signals! AND, OR, ... are great for these type but almost everything else should be a signed or unsigned type (or even an integer for simple counters and the like).