Usually its a good idea to tell the exact error message...

What libraries do you use?
As a hint: most probably you have a problem with types.
1. A array index MUST be a integer
2. You cannot simply multiply a vector with an integer

Hi Lothar,

Thanks for the reply. Yes, there is a problem with types.

Ok, so after converting to integers, it compiles, thanks. Is there a 
better/more concise way to access an 8 bit vector within a longer 
std_logic_vector than the following?

1

tempByte_from_byte_aligned := byteData((to_integer(unsigned(byteIndex)) * 8 + 7) downto (to_integer(unsigned(byteIndex)) * 8));

2

tempByte_from_bit_aligned = bitData((to_integer(unsigned(bitIndex))+7) downto to_integer(unsigned(bitIndex)));

This is the info related to your reply, though not relevant anymore.

The errors for the line beginning "tempData :=" are:

1

Error (10327): VHDL error at ...: can't determine definition of operator ""*"" -- found 0 possible definitions

2

Error (10327): VHDL error at ...: can't determine definition of operator ""+"" -- found 0 possible definitions

3

Error (10476): VHDL error at ...: type of identifier "bitIndex" does not agree with its usage as "natural" type

My libraries are:

1

library  ieee;

2

use ieee.std_logic_1164.all;

3

use ieee.std_logic_unsigned.all;

4

use ieee.numeric_std.all;

Cheers,
Dave

First: kick off the std_logic_unsigned.
Because together with the recommended numeric_std you can get double and 
ambiguous definitions for some operations...

Second: don't calculate with unconstrained vectors!
Use unsigned signals instead of std_logic vectors!
(and of course: with the numeric_std you cannot do calculations with 
vectors! You must cast the vector to signed or unsigned before 
calculations)

> Second: don't calculate with unconstrained vectors!
Why not? The few examples I've seen do it frequently. Are bitwise 
operations ok with vectors?

> Use unsigned signals instead of std_logic vectors!
> (and of course: with the numeric_std you cannot do calculations with
> vectors! You must cast the vector to signed or unsigned before
> calculations)
I did that and it compiles. I now have my entity's port input/output as 
std_logic and std_logic_vector, my variables and signals as unsigned 
(except my bitData array which is a constant std_logic_vector)... is 
this all ok?

Thanks again for your time :)

David Atol wrote:
>> Second: don't calculate with unconstrained vectors!
> Why not? The few examples I've seen do it frequently.
Get a book from P. Ashenden (they're good) and you won't see 
std_logic_arith in there.

Just a little test: what number is "1001"?
Is it 9? Or is it -7?

What number is unsigned "1001"?
It is 9!

And most problematic is the multiplication: a signed mult is much 
different than a unsigned mult.
And so, all in all: don't do calculations with unconstrained vectors. 
Even if you can find it in a lot of books from the last millennium...

> Are bitwise operations ok with vectors?
Of course they are...

Lothar Miller wrote:
> Get a book from P. Ashenden (they're good) and you won't see
> std_logic_arith in there.
Ok I got one from last decade based on the one from last millennium... 
;p

>> Are bitwise operations ok with vectors?
> Of course they are...
As I thought. It makes sense that it should be fine for 
add/subtract/rotate/logical-shift but not mult/div/arithmetic-shift due 
to how the sign is handled.

Ok, thanks very much for your help.