code snipets:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TEST is port (
addr : in integer range 0 to 31;
end TEST;
component TEST port (
addr : in integer range 0 to 31;
end component;
DBUS : inout std_logic_vector(15 downto 0);
Inst_TEST: TEST port map (
addr => to_integer(unsigned(DBUS(4 downto 0))),
);
This is where I get the ISE error:
Actual, ParameterAssocOp, associated with
Formal Signal, Signal 'addr', is not a Signal. (LRM 2.1.1)
What am I doing wrong here?
> What am I doing wrong here?
Mapping "inout" to "in" port?
Try it with a local signal:
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In this way no function or procedure is called within the port assignment...
Peter K. wrote: > Mapping "inout" to "in" port? No, that wasn't the problem...
And what was the problem?
Lothar Miller wrote: > In this way no function or procedure is called within the port > assignment... Thats it, thanks. "You can't put the conversion right in the port mapping." http://forums.xilinx.com/t5/Synthesis/numeric-std-std-logic-vector-to-integer/td-p/245590
Lothar Miller wrote: > And what was the problem? I intended to reply to both you and Peter at the same time, but got interrupted in between.