i try to do the vhdl code for 3 bit multiplier but i getting confuse and confuse when try to create the code can someone help me??
Let the VHDL compiler make it for you. ... signal a:integer range 0 to 7:=5 ; signal b:integer range 0 to 7:=6; signal c:integer range 0 to 16 :=7; signal result : integer range 0 to 127; ... begin Timer: process (Clock_50MHz) is begin if rising_edge(Clock_50MHZ) then result <= a*b+c; a <= a -1; end if; end process; ...
ehhh...dun understand....i using quartus 2 altera web edition, can it make something like this??
Why do you not check it out? Enter your code and let quartus synthesize it! Where ist the problem to test it out?
hor chin wrote: > can someone help me?? Show what you have and report whats the problem with it. Then someone might help you, but we intend not to do your homework completely...
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