Hi Folks, I need help to mod the code for this FPGA based (Altera CycloneII EP2C5T144) Digital Peak Level Meter: http://www.beis.de/Elektronik/DPLCM/DPLCM.html The code is available at the bottom of the page. The problem: I don't need the SPDIF feature, so I would like to implement an I2S input, which would be directly connected to the output of the A/D Converter. The I2S lines are: BCK (Serial Bit Clock) WS (Word Select, or LRCLK) SDI (Audio Serial Data Input) The I2S timing and standard description can be found at: http://www.classic.nxp.com/acrobat_download2/various/I2SBUS.pdf Can anyone help? Thanks in advance.
> Can anyone help? Cut out the SPDIF-Rx.vhd and replace it by your I2S-Rx.vhd Inside this I2S-Rx.vhd you have to implement the I²S decoder. And thats fairly simple: for sure the I²S decoder will cost less than 50 lines of code... Data afterwards is passed to the upper level module by AudioData0 : out std_logic_vector(23 downto 0); AudioData1 : out std_logic_vector(23 downto 0); > Can anyone help? With what? Pls ask more specific questions instead of "who can do my work?"
Lothar Miller wrote: >> Can anyone help? > Cut out the SPDIF-Rx.vhd and replace it by your I2S-Rx.vhd > Inside this I2S-Rx.vhd you have to implement the I²S decoder. And thats > fairly simple: for sure the I²S decoder will cost less than 50 lines of > code... > > Data afterwards is passed to the upper level module by > AudioData0 : out std_logic_vector(23 downto 0); > AudioData1 : out std_logic_vector(23 downto 0); > >> Can anyone help? > With what? > Pls ask more specific questions instead of "who can do my work?" Who can do my work: I should have been clearer: I'm not a programmer, it's not my work. I wouldn't know where to start. So the help is for the code itself.
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Did you manage to run the I2S Interface? This would be interesting to my too.