> can any 1 help me in writing a code for 6 to 16 bit programmable
> parallel to serial converter.......
Maybe. What do you have already done? Show your work and then ask your 
questions.

> for 6 to 16 bit programmable parallel to serial converter.
Is that a simple loadable shift register?
Draw a picture or just add more information.

> ......
You should have a close look on your dot key. Maybe its stuck.

i attatched my code what i have written so plz check it out and say me 
where should i modify

A loop is the totally wrong way.
A loop in VHDL implements several instances of the described part inside 
the loop in parallel. It does something completely different than a 
loop in C. What you need is a counter and a schift register...


This here is a little bit tricky:

1

process( clk)

2

variable x : integer := 6;

3

begin

4

  if DataReady = '1' then    -- DataReady is missing in the sensitivity list

5

     if (clk'event and clk = '1') then

This you should write that way (as anyone else in the world does):

1

process( clk)

2

variable x : integer := 6;

3

begin

4

  if (clk'event and clk = '1') then   -- FIRST there has to be a clock!

5

     if DataReady = '1' then

And: you will not need a variable for this simple task.
A variable also does not do that what you expect...


BTW: attach your code as a *.vhdl file (not as *.txt) and you will see a 
little magic...

so plzzzz help me still where should i modify the code to get the 
appropriate result without using a variable.....

Let me say its a fairly simple task.
I'm really astonished about your problems....  :-o

Try to understand this:

1

library IEEE;

2

use IEEE.STD_LOGIC_1164.ALL;

3

use IEEE.STD_LOGIC_ARITH.ALL;

4

use IEEE.STD_LOGIC_UNSIGNED.ALL;

5

6

7

entity P2S is

8

port ( Serial_out     : out std_logic;

9

       clk            : in std_logic;

10

       Parallel_data  : in std_logic_vector(15 downto 0);

11

       DataReady      : in std_logic);

12

13

end P2S;

14

15

architecture Behavioral of P2S is

16

17

signal OldReady : std_logic := '0';

18

signal Shreg    : std_logic_vector( 15 downto 0);

19

20

begin

21

22

  process (clk) begin

23

    if (clk'event and clk = '1') then

24

      Shreg <= '0' & Shreg(15 downto 1);     -- shift it left to right

25

      if DataReady='1' and OldReady='0' then -- rising edge = new data

26

        Shreg <= parallel_data;              -- load it

27

      end if;

28

    end if;

29

  End process;

30

31

  Serial_out <= Shreg(0);

32

33

end Behavioral;

I use a little trick so that its not necessary for me to check the 
length: if all of the bits are transmitted, with evere clock a '0' is 
shifted out.

ya it is fine but nw here if we get 16 bit data dat is geting serialized 
but sometimes i may get 6 bit r 8 bit r 10 bit r etc at dat time dat can 
get into serialized. How this can be known according to ur logic........

> How this can be known according to ur logic...
Nobody can know that. Because there is no information how much of the 16 
bits contain "real" data. Lets take the word "0000_1001_0011_0001". Is 
it 12 bits or 16 bits long?
Lets transmit 6 bit like this: "110011"? How will it look like?

1

clk  _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

2

data _______________----____----_____________

Where does the frame start?
Whats the difference to a 8 bit word like "00110011"? How does this look 
like? Tahke this:

1

clk  _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

2

data _______________----____----_____________

You see: you cannot see a difference!

So usually you will need a frme signal that tells you, when a telegram 
starts and when it ends. Then you can easily seen how long the data 
telegram is:

1

clk  _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

2

data _______________----____----_____________

3

frame __________----------------_____________

This was 8 bits.

1

clk  _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

2

data _______________----____----_____________

3

frame ______________------------_____________

And this was 8 bits.

The whole thing is realized like a SPI interface.

so wt ever the length of the data we get, that will get serialized 
according to this logic and but here you took 16 bit if i get the data 
of 8 r 10 bit length of data so that many bits get serialized and gives 
the output?

Did not get your question...  :-/

> if i get the data of 8 r 10 bit length
What would you input to the P2S unit?
The input port has 16 bit witdh:

1

entity P2S is

2

port ( ....

3

       Parallel_data  : in std_logic_vector(15 downto 0);

How do you go into this unit with 8 or 10 bits?

ya input is fixed length of 16 bit but this parallel to serial converter 
logic should be programmable when ever the data will arrive then dat 
should get serialized. For example 1st i got the data of 6 bit length at 
that time that data should be latched then it should get serialized. 
Similarly some other time when i get the data of length10 bit even in 
same way that should get serialized. This means our logic should be 1 
time programmed instead of runtime programmable......... I think u got 
my point

Iam attatching one more file it is nt simulating i have written this 
type also so Once check this also compare my previous reply  and say me 
plzzzz........

> For example 1st i got the data of 6 bit length at
> that time that data should be latched then it should get serialized.
> Similarly some other time when i get the data of length10 bit even in
> same way that should get serialized.
Thats exactly, what my previously posted code does...

> 1st i got the data of 6 bit length
> some other time when i get the data of length10 bit even in same way
And HOW can cou see this difference of 4 bits on a 16 bit vector?
How can you KNOW the witdh of the actual vector?

> I think u got my point
Yes, i do, but not vice versa.
Draw a picture with different parallel input vectors and how the have to 
occur on the serial output...

EDIT:
> it is nt simulating
Why? Whats the problem?
>  counter<=counter+1;
Counter is an integer. And an integer can get much higher values than 
the index here will be allowed to:
> Serial_out<=Parallel_data(counter);

ya if we get 6 bit data at that time as we have given fixed length is 16 
bit in that it takes 6 bit of data and remaining will send as zeros 
without affecting the data. This way it will happen  na?

> This way it will happen  na?
Yes. Try it with a simulation...

Thank you so much for your support. your posts are helped me alot

here is another method to design parallel to serial converter

http://appliedelectronicsengineering.blogspot.com/2014/12/parallel-to-serial-vhdl-code-with.html

this is much easier to understand