library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity P2S is
port ( Serial_out : out std_logic;
        clk       : in std_logic;
   Parallel_data  : in std_logic_vector(15 downto 0);
	DataReady      : in std_logic);
   
end P2S;

architecture Behavioral of P2S is

Signal Shreg : std_logic_vector( 15 downto 0);


begin

process( clk)
variable x : integer := 6;

begin
 

  if DataReady = '1' then
   
if (clk'event and clk = '1') then

x := x+1;
for i in 0 to x loop
if(parallel_data = i) then
Shreg <= parallel_data;
else
Shreg <= Shreg(0) & Shreg(x downto 1);
end if;
end loop;
end if;
else
Serial_out <= Shreg(0);


End if;

End process;


End Behavioral;

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ERROR:Xst:1549 - "D:/Anjali/DATA ACQISITION/p2s/p2s.vhd" line 51: Range bound must be a constant.