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Problem with clock in FPGA
von Vineela T. (Company: Efftronics Sys Pvt Ltd) (vineela)

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Is there any relation ship between clock and output? Actually i'm using 
PLL to generate clock of any frequency(1.5 to 350MHz) and using that 
clock as a reference for the code.

If I use sclk freq of 14MHz and i'm changing the upperlimit of count 
value (indicated using comments in the code) then the real output is not 
as post synthesis simulated output.

ie it works when count="0001000100010111000000" and it is not working 
when count ="0000111110001001010001" in the if condition.


please help....

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Re: Problem with clock in FPGA
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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> ie it works when count="0001000100010111000000" and it is not working
> when count ="0000111110001001010001" in the if condition.
Why do you not count with integers? Then you can write
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        if(count>0 and count<49) then  ...

instead of
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        if(count>"000000000000000000000" and count<"000000000000000110001") then ...



You have a VERY UNUSUAL way to describe clocked processes:
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process(temp1,reset,templock)

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begin

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    if(reset='1' and templock='1') then

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        if(count>"000000000000000000000" and count<"000000000000000110001") then

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            if falling_edge(temp1) then  --- Huh, a clock. Here?


Additionally you muddle up combinational and clocked processes. And you 
also have two clocks in one process:
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process(temp1,data,intaddr,reset,templock)

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begin

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    if(reset='1' and templock='1') then               -- first combinational

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        if(count>"000000000000000000000" and count<"000000000000000110001") then

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            if rising_edge(temp1) then                -- then a clock

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                :

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            end if;

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        elsif(count = "000000000000000110001") then   -- then combinational

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            if rising_edge(temp1) then                -- and again a clock

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                :

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                intaddr<=intaddr+1;

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            end if;

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        else                                          -- further on combinational

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            :

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            data<=LETTER_DB(conv_integer(intaddr));            

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        end if;        

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    else                                             

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        intaddr <= "0000000"; 

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        :

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    end if;

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end process;

I urge you to have a close look how others are doing it. Although your 
description may work (because synthesizers get better each day), you 
will NOT see this style in any book!

>  if rising_edge(temp1) then
>  if falling_edge(temp1) then
In a synchronous design there is only 1 clock. Thats the "one and only" 
system clock. And the whole design uses the same edge of this clock. 
temp1 sounds not like a system clock...  :-/

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