-- scroll_29_02.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity scrolling_text is port ( clk: in std_logic; --clock to the fpga reset: in std_logic; --reset is to clear the display board sclk: out std_logic; --serial clock to the sram sdi: out std_logic_vector(3 downto 0):="0000"; --serial data input to the display board le_d: out std_logic:='0'; --le to the display board oe_d: out std_logic:='0' --oe to the display board ); end scrolling_text; architecture arch_scrolling of scrolling_text is component pll_29_02 is port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out std_logic) ; end component; --48 coloumns data for the display board signal c1: std_logic_vector(7 downto 0):="00000000"; signal c2: std_logic_vector(7 downto 0):="00000000"; signal c3: std_logic_vector(7 downto 0):="00000000"; signal c4: std_logic_vector(7 downto 0):="00000000"; signal c5: std_logic_vector(7 downto 0):="00000000"; signal c6: std_logic_vector(7 downto 0):="00000000"; signal c7: std_logic_vector(7 downto 0):="00000000"; signal c8: std_logic_vector(7 downto 0):="00000000"; signal c9: std_logic_vector(7 downto 0):="00000000"; signal c10: std_logic_vector(7 downto 0):="00000000"; signal c11: std_logic_vector(7 downto 0):="00000000"; signal c12: std_logic_vector(7 downto 0):="00000000"; signal c13: std_logic_vector(7 downto 0):="00000000"; signal c14: std_logic_vector(7 downto 0):="00000000"; signal c15: std_logic_vector(7 downto 0):="00000000"; signal c16: std_logic_vector(7 downto 0):="00000000"; signal c17: std_logic_vector(7 downto 0):="00000000"; signal c18: std_logic_vector(7 downto 0):="00000000"; signal c19: std_logic_vector(7 downto 0):="00000000"; signal c20: std_logic_vector(7 downto 0):="00000000"; signal c21: std_logic_vector(7 downto 0):="00000000"; signal c22: std_logic_vector(7 downto 0):="00000000"; signal c23: std_logic_vector(7 downto 0):="00000000"; signal c24: std_logic_vector(7 downto 0):="00000000"; signal sdi_1: std_logic_vector(47 downto 0); signal sdi_3: std_logic_vector(47 downto 0); signal sdi_5: std_logic_vector(47 downto 0); signal sdi_7: std_logic_vector(47 downto 0); signal temp1: std_logic; signal count: std_logic_vector(20 downto 0):="000000000000000000000"; signal intaddr: std_logic_vector(6 downto 0):="0000000"; constant temp: std_logic_vector(7 downto 0):="00000000"; signal data: std_logic_vector(7 downto 0); signal templock,tempgla: std_logic; type rom_type is array (0 to 127) of std_logic_vector(7 downto 0); constant LETTER_DB: rom_type := ( "00000000", "00000000", "01111110", "00000010", "00000100", "00001000", "00000100", "00000010", "01111110", "00000000", "00000000", "01111110", "01010010", "01010010", "01000010", "00000000", "00000000", "01111110", "00000010", "00000010", "00000010", "00000000", "00000000", "00111100", "01000010", "01000010", "01000010", "00000000", "00000000", "00111100", "01000010", "01000010", "00111100", "00000000", "00000000", "01111110", "01000000", "00100000", "00010000", "00100000", "01000000", "01111110", "00000000", "00000000", "01111110", "01010010", "01010010", "01000010", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000" ); begin PLL1: pll_29_02 port map( POWERDOWN => reset, CLKA => clk, LOCK => templock, GLA => tempgla ); process(tempgla,temp1,templock) begin if(reset='1') then if(templock='1') then if rising_edge(tempgla) then temp1<= temp1 xor '1'; end if; else temp1<='0'; end if; else temp1<='0'; end if; end process; process(temp1,data,intaddr,reset,templock) begin if(reset='1' and templock='1') then if(count>"000000000000000000000" and count<"000000000000000110001") then if rising_edge(temp1) then sdi_1(47 downto 0) <= sdi_1(46 downto 0) & sdi_1(47); sdi_3(47 downto 0) <= sdi_3(46 downto 0) & sdi_3(47); sdi_5(47 downto 0) <= sdi_5(46 downto 0) & sdi_5(47); sdi_7(47 downto 0) <= sdi_7(46 downto 0) & sdi_7(47); end if; elsif(count = "000000000000000110001") then if rising_edge(temp1) then c1 <= c2; c2 <= c3; c3 <= c4; c4 <= c5; c5 <= c6; c6 <= c7; c7 <= c8; c8 <= c9; c9 <= c10; c10 <= c11; c11 <= c12; c12 <= c13; c13 <= c14; c14 <= c15; c15 <= c16; c16 <= c17; c17 <= c18; c18 <= c19; c19 <= c20; c20 <= c21; c21 <= c22; c22 <= c23; c23 <= c24; c24 <= data; intaddr<=intaddr+1; end if; else sdi_1(47 downto 0) <= c24(1) & c23(1) & c22(1) & c21(1) & c20(1) & c19(1) & c18(1) & c17(1) & c17(0) & c18(0) & c19(0) & c20(0) & c21(0) & c22(0) & c23(0) & c24(0) & c16(1) & c15(1) & c14(1) & c13(1) & c12(1) & c11(1) & c10(1) & c9(1) & c9(0) & c10(0) & c11(0) & c12(0) & c13(0) & c14(0) & c15(0) & c16(0) & c8(1) & c7(1) & c6(1) & c5(1) & c4(1) & c3(1) & c2(1) & c1(1) & c1(0) & c2(0) & c3(0) & c4(0) & c5(0) & c6(0) & c7(0) & c8(0); sdi_3(47 downto 0) <= c24(3) & c23(3) & c22(3) & c21(3) & c20(3) & c19(3) & c18(3) & c17(3) & c17(2) & c18(2) & c19(2) & c20(2) & c21(2) & c22(2) & c23(2) & c24(2) & c16(3) & c15(3) & c14(3) & c13(3) & c12(3) & c11(3) & c10(3) & c9(3) & c9(2) & c10(2) & c11(2) & c12(2) & c13(2) & c14(2) & c15(2) & c16(2) & c8(3) & c7(3) & c6(3) & c5(3) & c4(3) & c3(3) & c2(3) & c1(3) & c1(2) & c2(2) & c3(2) & c4(2) & c5(2) & c6(2) & c7(2) & c8(2); sdi_5(47 downto 0) <= c24(5) & c23(5) & c22(5) & c21(5) & c20(5) & c19(5) & c18(5) & c17(5) & c17(4) & c18(4) & c19(4) & c20(4) & c21(4) & c22(4) & c23(4) & c24(4) & c16(5) & c15(5) & c14(5) & c13(5) & c12(5) & c11(5) & c10(5) & c9(5) & c9(4) & c10(4) & c11(4) & c12(4) & c13(4) & c14(4) & c15(4) & c16(4) & c8(5) & c7(5) & c6(5) & c5(5) & c4(5) & c3(5) & c2(5) & c1(5) & c1(4) & c2(4) & c3(4) & c4(4) & c5(4) & c6(4) & c7(4) & c8(4); sdi_7(47 downto 0) <= c24(7) & c23(7) & c22(7) & c21(7) & c20(7) & c19(7) & c18(7) & c17(7) & c17(6) & c18(6) & c19(6) & c20(6) & c21(6) & c22(6) & c23(6) & c24(6) & c16(7) & c15(7) & c14(7) & c13(7) & c12(7) & c11(7) & c10(7) & c9(7) & c9(6) & c10(6) & c11(6) & c12(6) & c13(6) & c14(6) & c15(6) & c16(6) & c8(7) & c7(7) & c6(7) & c5(7) & c4(7) & c3(7) & c2(7) & c1(7) & c1(6) & c2(6) & c3(6) & c4(6) & c5(6) & c6(6) & c7(6) & c8(6); data<=LETTER_DB(conv_integer(intaddr)); end if; else intaddr <= "0000000"; c24 <= temp; c23 <= temp; c22 <= temp; c21 <= temp; c20 <= temp; c19 <= temp; c18 <= temp; c17 <= temp; c16 <= temp; c15 <= temp; c14 <= temp; c13 <= temp; c12 <= temp; c11 <= temp; c10 <= temp; c9 <= temp; c8 <= temp; c7 <= temp; c6 <= temp; c5 <= temp; c4 <= temp; c3 <= temp; c2 <= temp; c1 <= temp; end if; end process; process(temp1,reset,templock) begin if(reset='1' and templock='1') then if(count>"000000000000000000000" and count<"000000000000000110001") then if falling_edge(temp1) then sdi <= sdi_7(47) & sdi_5(47) & sdi_3(47) & sdi_1(47); end if; end if; end if; end process; process(reset,count,temp1) begin if(reset='1' and templock='1') then if falling_edge(temp1) then count<=count+1; end if; if(count >"000000000000000000000" and count <"000000000000000110001") then le_d <= '0'; sclk <= temp1; elsif(count="000000000000000110111") then sclk <='Z'; le_d <='1'; elsif(count="000111110001001010001") then --upperlimit of count count<="000000000000000000000"; sclk <='Z'; le_d <='0'; else le_d<='0'; sclk <= 'Z'; end if; else le_d <= '0'; sclk <= 'Z'; count<="000000000000000000000"; end if; end process; end arch_scrolling;