help needed in top level creation

hi,

i am very new to vhdl coding. so, i  need some help in creating the top 
level for two sub modules. i have written the following code for it.

------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;

entity system is
Port ( clk : in STD_LOGIC;
       reset : in STD_LOGIC;
       tdata_in : in std_logic_vector(7 downto 0);
       tdata_out : out std_logic_vector(7 downto 0)
       );
end system;

architecture Behavioral of system is

component InternalADC is
    port (
        reset     : in  std_logic;
        clk       : in  std_logic;
        wr        : in  std_logic;
        rd        : in  std_logic;
        addr      : in  std_logic_vector(7 downto 0);
        data_in   : in  std_logic_vector(7 downto 0);
        data_out  : out std_logic_vector(7 downto 0);
        miso      : in  std_logic;
        next_mosi : out std_logic;
        next_sck  : out std_logic;
        cen       : out std_logic;
        EOC       : in  std_logic;
        PowDownAD : out std_logic
    );
end component;

component afsk is
    Port (
            Clk : in  STD_LOGIC;
            reset : in  STD_LOGIC;
          bfs1 : in std_logic_vector(19 downto 0);
            bdata_in : in  std_logic_vector (7 downto 0);
            bdata_out : out  STD_LOGIC
        );
end component;


signal bfs1 : std_logic_vector (19 downto 0);
signal data_int : std_logic_vector (7 downto 0);

begin

a : InternalADC PORT MAP (clk, reset, wr, rd, addr, miso, next_mosi, 
next_sck, cen, EOC, PowDownAD,
                           data_in => tdata_in,
                           data_out => data_int);

b : afsk PORT MAP ( bfs1, clk, reset, data_int, bdata_out => tdata_out);


end;
------------------------------------------------------------------------ 
-
------------------------------------------------------------------------ 
-

but it gives me the following errors when i simulate it...
-----------------------------------------------------------

# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(52): (vcom-1028) Formal 
"data_in" has already been associated in a positional association.
# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(53): (vcom-1028) Formal 
"data_out" has already been associated in a positional association.
# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(53): VHDL Compiler exiting
# ** Error: C:/Actel/Libero_v9.1/Model/win32acoem/vcom failed.
# Error in macro ./run.do line 14

please help me with this problem..