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Verilog Design
von littlestewie (Guest)

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hi,
I am trying to create a simple cpu using verilog but i couldn't.
I am using a logisim circuit as starting point.

This is the cpu desing.
http://a1202.hizliresim.com/u/v/31szg.png

This is the control unit
http://c1202.hizliresim.com/u/r/2yrng.png


i have added four important modules of this project.

This code doesn't work . Where is the problem?

thanks for any help

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Re: Verilog Design
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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> Where is the problem?
What does the simulation say?

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Re: Verilog Design
von littlestewie (Guest)

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how can i run a simulation,

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Re: Verilog Design
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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> how can i run a simulation,
Depends on your toolchain...

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Re: Verilog Design
von littlestewie (Guest)

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i am using altera de2 fpga board and
quartus ii web edition

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