Verilog Design

hi,
I am trying to create a simple cpu using verilog but i couldn't.
I am using a logisim circuit as starting point.

This is the cpu desing.
http://a1202.hizliresim.com/u/v/31szg.png

This is the control unit
http://c1202.hizliresim.com/u/r/2yrng.png


i have added four important modules of this project.

This code doesn't work . Where is the problem?

thanks for any help