hi, I am trying to create a simple cpu using verilog but i couldn't. I am using a logisim circuit as starting point. This is the cpu desing. http://a1202.hizliresim.com/u/v/31szg.png This is the control unit http://c1202.hizliresim.com/u/r/2yrng.png i have added four important modules of this project. This code doesn't work . Where is the problem? thanks for any help
> Where is the problem? What does the simulation say?
how can i run a simulation,
> how can i run a simulation, Depends on your toolchain...
i am using altera de2 fpga board and quartus ii web edition