module simplecpu ( input clk, output wire s_out0, output wire s_out1, output wire s_out2, output wire s_out3, output wire s_out4, output wire s_out5, output wire s_out6, output wire s_out7 ); wire w_arload,w_pcload,w_pcinc,w_drload,w_acload,w_acinc,w_irload,read,drbus,pcbus,membus,alusel; wire [5:0] win_ar,win_pc,w_ar_to_mem,pc_to_bus; wire [7:0] win_dr,win_dr_alu,win_ac_alu,win_ac,data_bus,dr_to_bus,mem_to_bus; wire[1:0] win_ir,irtorom; wire [11:0] fromcontrol;//0 read,11 arload assign read = fromcontrol[0]; assign drbus = fromcontrol[1]; assign pcbus = fromcontrol[2]; assign membus = fromcontrol[3]; assign alusel = fromcontrol[4]; assign w_irload = fromcontrol[5]; assign w_acinc = fromcontrol[6]; assign w_acload = fromcontrol[7]; assign w_drload = fromcontrol[8]; assign w_pcinc = fromcontrol[9]; assign w_pcload = fromcontrol[10]; assign w_arload = fromcontrol[11]; controlunit mycontrol (.clk(clk), .ir(irtorom), .controls(fromcontrol)); alu myalu (.ac(win_ac_alu), .dr(win_dr_alu), .sel(alusel), .toAC(win_ac)); ar_register my_ar (.out(w_ar_to_mem), .in(win_ar), .arload(w_arload), .clk(clk)); pc_register my_pc (.out(pc_to_bus), .in(win_pc), .pcload(w_pcload), .clk(clk), .pcinc(w_pcinc)); dr_register my_dr (.out(dr_to_bus), .in(win_dr), .drload(w_drload), .clk(clk)); ac_register my_ac(.out(win_ac_alu), .in(win_ac), .acload(w_acload), .acinc(w_acinc), .clk(clk)); ir_register my_ir(.out(irtorom), .in(win_ir), .irload(w_irload), .clk(clk)); main_rom my_rom (.address(w_ar_to_mem), .data(mem_to_bus)); assign s_out0 = win_ac_alu[0]; assign s_out1 = win_ac_alu[1]; assign s_out2 = win_ac_alu[2]; assign s_out3 = win_ac_alu[3]; assign s_out4 = win_ac_alu[4]; assign s_out5 = win_ac_alu[5]; assign s_out6 = win_ac_alu[6]; assign s_out7 = win_ac_alu[7]; assign win_ar[5:0] = data_bus[5:0]; assign win_pc[5:0] = data_bus[5:0]; assign win_dr[7:0] = data_bus[7:0]; assign win_ir[1:0] = data_bus[7:6]; assign data_bus = (membus) ? mem_to_bus : 8'bz; assign data_bus [5:0] = (pcbus) ? pc_to_bus : 6'bz; assign data_bus = (drbus) ? dr_to_bus : 8'bz; endmodule