This error on quartus: formal port or parameter "N" must have actual or
default value
What does it mean?
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity shrBbits is
generic (N:positive);
port( A,B: in std_logic_vector(N-1 downto 0);
OP: in std_logic_vector(2 downto 0);
RES_LO:out std_logic_vector(N-1 downto 0)
);
end entity;
I have this code:
Doing a shift to A - B times.
entity shrBbits is
generic (N:positive:=32);
port( A,B: in std_logic_vector(N-1 downto 0);
OP: in std_logic_vector(2 downto 0);
RES_LO:out std_logic_vector(N-1 downto 0)
);
end entity;
architecture behv of shrBbits is
signal temp,temp_res: std_logic_vector(N-1 downto 0);
signal num:integer:=0;
begin
process (A,B,OP,num,temp,temp_res)
begin
temp<=A;
temp_res<=A;
if (conv_integer(B)<0) then --for negative B
num<=conv_integer(not (B))+1;
else if num=0 then
temp_res<=A;
num<=conv_integer(B);
else
num<=conv_integer(B);
end if;
end if;
temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE
ERROR
temp_res(num downto 0)<=temp(N-1 downto num);
RES_LO<=temp_res;
end process;
end behv;
How can it be changed?
Yes - thanks - you right
it should be:
temp_res(N-1 downto N-num)<= temp(num-1 downto 0);
temp_res(N-num-1 downto 0)<=temp(N-1 downto num);
But it still gives me the same error.
Why?
> Doing a shift to A - B times.
Really a shift?
A right shift or a left shift?
Or (as you do) a rotation?
With your name sh-r-B-bits I assume a right shift for B bits:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity shrBbits isgeneric (N:positive:=32);
port( A,B: instd_logic_vector(N-1downto0); -- why is B that big? 6 bits (0..32) would be enough!!!
OP: instd_logic_vector(2downto0); -- what is this OP good for?
RES_LO:outstd_logic_vector(N-1downto0)
);
endentity;
architecture behv of shrBbits issignal num : integerrange0to2*N:=0;
signal hlp : std_logic_vector(N*2-1downto0);
begin-- used ressources and delay times are for a Spartan 3 AN-- Number of Slices 75-- Maximum combinational path delay: 10.832nsprocess (A,B)
variable h : std_logic_vector(N-1downto0);
variable c : integerrange0to N:=0;
begin
h := A;
c := to_integer(unsigned(B));
for i in0to N-1loopif i<c then
h := '0' & h(N-1downto1);
endif;
endloop;
RES_LO <= h;
endprocess;
-- Number of Slices 75-- Maximum combinational path delay: 10.912nsprocess (A,B)
variable h : std_logic_vector(N-1downto0);
variable c : integerrange0to N:=0;
begin
h := A;
c := to_integer(unsigned(B));
for i in0to N-1loopif i=c thenexit;
endif;
h := '0' & h(N-1downto1);
endloop;
RES_LO <= h;
endprocess;
-- Number of Slices 79-- Maximum combinational path delay: 11.445nsprocess (A,B)
variable h : std_logic_vector(N-1downto0);
variable c : integerrange0to N:=0;
begin
c := to_integer(unsigned(B));
h := (others=>'0');
h(N-1-c downto0) := A(N-1downto c);
RES_LO <= h;
endprocess;
-- Number of Slices 82-- Maximum combinational path delay: 11.536ns
num <= to_integer(unsigned(B));
hlp <= x"00000000"&A;
RES_LO <= hlp(N-1+num downto num);
end behv;
The last one can easily be changed to a rotate function:
For
process (A,B)
variable h : std_logic_vector(N-1 downto 0);
variable c : integer range 0 to N:=0;
begin
c := to_integer(unsigned(B));
h := (others=>'0');
h(N-1-c downto 0) := A(N-1 downto c);
RES_LO <= h;
end process;
I still have an error "right bound of range must be constant".
What else might it be
Here is the full code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.pack.all;
-- this unit shift A bits number of B times to the right
-- if B is negative or zero the result is still A
-- the result is in res_shr
entity shrBbits is
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
RES_SHR:out std_logic_vector(N-1 downto 0)
);
end entity;
architecture behv of shrBbits is
begin
process (A,B)
variable h : std_logic_vector(N-1 downto 0);
variable c : integer range 0 to N:=0;
begin
c := conv_integer(unsigned(B));
h := (others=>'0');
h(N-1-c downto 0) := A(N-1 downto c);
RES_SHR <= h;
end process;
end behv;
Thanks for the help,
Miri
> I still have an error "right bound of range must be constant".
What toolchain?
EDIT: too late... :-/
> I have this error while running Quartus
With Xilinx XST this works fine...
BTW: you did see this in my code?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Yes? Think about it...
A hint: the Synopsys libs are obsolete a long time ago and superseeded
by the numeric_std.
BTW2: with
[ vhdl]
and
[ /vhdl]
(but without the blanks) and you can see a little magic:
I'm not sure, but I think the problem with Quartus is:
h(N-1-c downto0) := A(N-1downto c);
ISE and Lattice Diamond can handle this, but Quartus may have a problem
with this statement.
You could try to use a 'for i in 0 to N-1 loop' and assign just bitwise
This error on quartus:Error (10346): VHDL error at accumu.vhd(18):
formal port or parameter "m" must have actual or default value
What does it mean?
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity acc isport(x,y: instd_logic_vector(3downto0);
selacc,selpm,key: instd_logic;
somme: outstd_logic_vector(3downto0));
endentity acc;
architecture structure of acc issignal x0,x1,x2: std_logic_vector(3downto0);
begin
u0: mux2to1 portmap(m0=>x,m1=>x1,mout=>x0, sel=>selacc);
u1 : adder4 portmap(a=>y,b=>x0, sel=>selpm, cout=>open,z=>1);
u2:registre portmap(clk=>key,d=>x1,q=>x2);
somme<=x2;
endarchitecture structure ;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity adder4 isport(m,n:instd_logic_vector(3downto0);
cin:instd_logic;
cout:outstd_logic;
p:outstd_logic_vector(3downto0));
endentity adder4;
architecture structure of adder4 issignal c0,c1,c2:std_logic;
begin
fa0: fa portmap(y=> m(0),x=> n(0),cin=>cin,s=>p(0),cout=>c0);
fa1: fa portmap(y=> m(1),x=> n(1),cin=>cin,s=>p(1),cout=>c1);
fa2: fa portmap(y=> m(2),x=> n(2),cin=>cin,s=>p(2),cout=>c2);
fa3: fa portmap(y=> m(3),x=> n(3),cin=>cin,s=>p(3),cout=>cout);
endarchitecture structure;
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 isport(m0,m1:instd_logic_vector(3downto0);
mout:outstd_logic_vector(3downto0);
sel:instd_logic);
endentity mux2to1;
architecture behavior of mux2to1 isbegin
mout<=m0 when (sel='0')else m1;
endarchitecture behavior;
Amina Amin wrote:> Here is my code
Why do you not use some indetion to get a kind of readable code...
> of course each i wrote each entity in a vhdl file
You can have it in one file also, thats no problem. Or you could attach
each of the files here, so it would be easier to find that line 18 in
accumu.vhd...
However: what about simply using the same names for the port signals in
the entity and in the port list?
u1 : adder4 portmap(a=>y, b=>x0, sel=>selpm, cout=>open,z=>1); -- a,b,sel,cout and zentity adder4 isport(m,n:instd_logic_vector(3downto0); -- m,n,cin,cout and p
cin:instd_logic;
cout:outstd_logic;
p:outstd_logic_vector(3downto0));
endentity adder4;