I have this code:
Doing a shift to A - B times.

entity shrBbits is
  generic (N:positive:=32);
  port( A,B: in std_logic_vector(N-1 downto 0);
        OP: in std_logic_vector(2 downto 0);
        RES_LO:out std_logic_vector(N-1 downto 0)
    );
end entity;

architecture behv of shrBbits is
signal temp,temp_res: std_logic_vector(N-1 downto 0);
signal num:integer:=0;
begin
  process (A,B,OP,num,temp,temp_res)
  begin
  temp<=A;
  temp_res<=A;
  if (conv_integer(B)<0) then --for negative B
    num<=conv_integer(not (B))+1;
  else if num=0 then
      temp_res<=A;
      num<=conv_integer(B);
     else
      num<=conv_integer(B);
     end if;
  end if;
  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE 
ERROR
  temp_res(num downto 0)<=temp(N-1 downto num);
  RES_LO<=temp_res;
  end process;
end behv;

How can it be changed?

>-- HERE IS THE ERROR
WHAT error?

1

  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE ERROR

No.
Your error happens much before!
How does a signal react in an process?
How does a variable react in a process?

However:

1

  temp_res(N-1 downto num+1)<= temp(num-1 downto 0); -- HERE IS THE ERROR

Calculate this for N=32 and lets say num=3:
  temp_res(31 downto 4)     <=     temp(2 downto 0);
   this vector ^^^^  is MUCH longer than  ^^^^ this vector...  :-o

Yes - thanks - you right

it should be:
  temp_res(N-1 downto N-num)<= temp(num-1 downto 0);
  temp_res(N-num-1 downto 0)<=temp(N-1 downto num);


But it still gives me the same error.

Why?

I have to do this task without clock?

It's strange to do it this way, but still, do you have some ideas to 
work it out?

thanks

No. B is positive.

> No. B is positive.
So, why that:

1

  if (conv_integer(B)<0) then --for negative B

> Doing a shift to A - B times.
Really a shift?
A right shift or a left shift?
Or (as you do) a rotation?

With your name sh-r-B-bits I assume a right shift for B bits:

1

library IEEE;

2

use IEEE.std_logic_1164.all;

3

use IEEE.numeric_std.all;

4

5

entity shrBbits is

6

  generic (N:positive:=32);

7

  port( A,B: in std_logic_vector(N-1 downto 0);  -- why is B that big? 6 bits (0..32) would be enough!!!

8

        OP: in std_logic_vector(2 downto 0);     -- what is this OP good for?

9

        RES_LO:out std_logic_vector(N-1 downto 0)

10

    );

11

end entity;

12

13

architecture behv of shrBbits is

14

signal num  : integer range 0 to 2*N:=0;

15

signal hlp  : std_logic_vector(N*2-1 downto 0);

16

begin

17

   --  used ressources and delay times are for a Spartan 3 AN

18

   --  Number of Slices 75

19

   --  Maximum combinational path delay: 10.832ns

20

   process (A,B) 

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   variable h : std_logic_vector(N-1 downto 0);

22

   variable c : integer range 0 to N:=0;

23

   begin

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      h := A;

25

      c := to_integer(unsigned(B));

26

      for i in 0 to N-1 loop

27

         if i<c then

28

            h :=  '0' & h(N-1 downto 1);

29

         end if;

30

      end loop;

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      RES_LO <= h;

32

   end process;

33

34

  -- Number of Slices 75

35

  -- Maximum combinational path delay: 10.912ns

36

  process (A,B) 

37

  variable h : std_logic_vector(N-1 downto 0);

38

  variable c : integer range 0 to N:=0;

39

  begin

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     h := A;

41

     c := to_integer(unsigned(B));

42

     for i in 0 to N-1 loop

43

        if i=c then

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           exit;

45

        end if;

46

        h := '0' & h(N-1 downto 1);

47

     end loop;

48

     RES_LO <= h;

49

  end process;

50

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  -- Number of Slices 79

52

  -- Maximum combinational path delay: 11.445ns

53

  process (A,B) 

54

  variable h : std_logic_vector(N-1 downto 0);

55

  variable c : integer range 0 to N:=0;

56

  begin

57

     c := to_integer(unsigned(B));

58

     h := (others=>'0');

59

     h(N-1-c downto 0) := A(N-1 downto c);

60

     RES_LO <= h;

61

  end process;

62

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  -- Number of Slices 82

64

  -- Maximum combinational path delay: 11.536ns

65

  num <= to_integer(unsigned(B));

66

  hlp <= x"00000000"&A;

67

  RES_LO <= hlp(N-1+num downto num);

68

69

end behv;

The last one can easily be changed to a rotate function:

1

   hlp <= A&A;

I tested the code above with the attached stimuli "testbench".

For
 process (A,B)
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     c := to_integer(unsigned(B));
     h := (others=>'0');
     h(N-1-c downto 0) := A(N-1 downto c);
     RES_LO <= h;
  end process;

I still have an error "right bound of range must be constant".

What else might it be

Here is the full code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.pack.all;

-- this unit shift A bits number of B times to the right
-- if B is negative or zero the result is still A
-- the result is in res_shr
entity shrBbits is
  port( A: in std_logic_vector(N-1 downto 0);
        B: in std_logic_vector(N-1 downto 0);
        RES_SHR:out std_logic_vector(N-1 downto 0)
    );
end entity;

architecture behv of shrBbits is
begin
  process (A,B)
  variable h : std_logic_vector(N-1 downto 0);
  variable c : integer range 0 to N:=0;
  begin
     c := conv_integer(unsigned(B));
     h := (others=>'0');
     h(N-1-c downto 0) := A(N-1 downto c);
     RES_SHR <= h;
  end process;

end behv;

Thanks for the help,
Miri

I have this error while running Quartus

> Here is the full code:
Lets say: except the missing definition of N...
I changed the code a little:

1

entity shrBbits is

2

  generic( N : integer := 16);

3

  port( .... );

4

end entity;

> I still have an error "right bound of range must be constant".
What toolchain?

EDIT: too late... :-/
> I have this error while running Quartus
With Xilinx XST this works fine...

BTW: you did see this in my code?

1

library IEEE;

2

use IEEE.std_logic_1164.all;

3

use IEEE.numeric_std.all;

Yes? Think about it...
A hint: the Synopsys libs are obsolete a long time ago and superseeded 
by the numeric_std.

BTW2: with
[ vhdl]
and
[ /vhdl]
(but without the blanks) and you can see a little magic:

1

and

Quartus 64 bits.

tool chain - modelsim

This error on quartus:Error (10346): VHDL error at accumu.vhd(18): 
formal port or parameter "m" must have actual or default value



What does it mean?


Here is my code:

1

library ieee;

2

use ieee.std_logic_1164.all;

3

library work;

4

use work.all;

5

entity acc is

6

port(x,y: in std_logic_vector(3 downto 0);

7

selacc,selpm,key: in std_logic;

8

somme: out std_logic_vector(3 downto 0));

9

end entity acc;

10

11

architecture structure of acc is

12

signal x0,x1,x2: std_logic_vector(3 downto 0);

13

14

begin

15

u0: mux2to1 port map(m0=>x,m1=>x1,mout=>x0, sel=>selacc);

16

u1 : adder4 port map(a=>y,b=>x0, sel=>selpm, cout=>open,z=>1);

17

u2:registre port map(clk=>key,d=>x1,q=>x2);

18

19

20

somme<=x2;

21

 end architecture structure ;

22

23

24

25

library ieee;

26

use ieee.std_logic_1164.all;

27

library work;

28

use work.all;

29

entity adder4 is

30

port(m,n:in std_logic_vector(3 downto 0);

31

cin:in std_logic;

32

cout:out std_logic;

33

p:out std_logic_vector(3 downto 0));

34

end entity adder4;

35

36

architecture structure of adder4 is

37

signal c0,c1,c2:std_logic;

38

begin

39

fa0: fa port map(y=> m(0),x=> n(0),cin=>cin,s=>p(0),cout=>c0);

40

fa1: fa port map(y=> m(1),x=> n(1),cin=>cin,s=>p(1),cout=>c1);

41

fa2: fa port map(y=> m(2),x=> n(2),cin=>cin,s=>p(2),cout=>c2);

42

fa3: fa port map(y=> m(3),x=> n(3),cin=>cin,s=>p(3),cout=>cout);

43

end architecture structure;

44

45

46

library ieee;

47

use ieee.std_logic_1164.all;

48

entity mux2to1 is

49

port(m0,m1:in std_logic_vector(3 downto 0);

50

mout:out std_logic_vector(3 downto 0);

51

sel:in std_logic);

52

end entity mux2to1;

53

architecture behavior of mux2to1 is

54

begin 

55

mout<=m0 when (sel='0')else m1;

56

end architecture behavior;

of course each i wrote each entity in a vhdl file

Amina Amin wrote:
> Here is my code
Why do you not use some indetion to get a kind of readable code...

> of course each i wrote each entity in a vhdl file
You can have it in one file also, thats no problem. Or you could attach 
each of the files here, so it would be easier to find that line 18 in 
accumu.vhd...

However: what about simply using the same names for the port signals in 
the entity and in the port list?

1

u1 : adder4 port map(a=>y, b=>x0, sel=>selpm, cout=>open,z=>1); -- a,b,sel,cout and z

2

3

entity adder4 is

4

port(m,n:in std_logic_vector(3 downto 0); -- m,n,cin,cout and p

5

cin:in std_logic;

6

cout:out std_logic;

7

p:out std_logic_vector(3 downto 0));

8

end entity adder4;