nightowl wrote:
> secret code?
Sercet simulation results?

> a 4bit X 3 bit multiplier.
Something like this?

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   signal y : unsigned (6 downto 0);

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   signal a : unsigned (3 downto 0);

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   signal b : unsigned (2 downto 0);

4

5

6

   y <= a*b;

No the code is not secret :) It is attached to this reply.
Thank you for the reply

> No the code is not secret :)
And the testbench?
What results do you get?

> architecture behaviour2 of multiplier4X3 is ...
Your description ist AVSOLUTY NOT a behavioural description. Ist a 
completly STRUCTURAL description. So why is the name of your architectur 
"behaviour2"?

BTW:
Why does everybody around the world write a half adder and a full adder 
and a multiplier (and even a AND gate...) on their own?
Why not just using the VHDL operators + AND *?

About the name that is correct my mistake, i should change it. Now about 
the half adder etc i wanted to do it like this so i can fresh my memory 
about vhdl.
About the code i tried to changed it a little and i added a new signal 
ztemp at the end of the code. The four lines named stage0-3 are replaced 
with

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stage0: fulladder4 port map (x(3 downto 0)=>k(3 downto 0), y(3 downto 0)=> l(3 downto 0),ztemp(3 downto 0)=>(z(3 downto 1)=>n(3 downto 1), z(0)=>P(1), Cout=>Cout1);

Still i get errors and i can't get it simulated like before, at all.
But here are the results of the simulation before, attached
Thank u!

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Attached files:

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    multiplier.vwf (8 KB, 0 downloads)

Could you pls attach screenshots as *.gif grphics?

> Still i get errors
What sort of ones?

I only have it on bmp type. Can you open it?
It keeps saying "Error (10348): VHDL type mismatch error at 
multiplier4X3.vhd(57): type of formal parameter "ztemp" does not match 
port type of value"

> I only have it on bmp type. Can you open it?
Yes. And you are right: it looks like complete nonsense...

Does your full adder work properly?
Whats the theory behind your multiplier?
Do you have a schematic (with your signal names in it)?