sreeram sam wrote:
> can anyone please give me a piece of vhdl code for stuck at faults
> stuck-at-0 and stuck-at-1 for any sequential and/or combination
> circuits, just need it to start from the scratch.
So you want to recognize a stucked/failed signal? Then define a 
stuck-at-1: how long must the signal be '1' to be stucked at '1'?

Or do you want to memorize a fault signal (even when the fault 
disapears) to see later, that there was a fault? Then you need a latch.

What do you want to do with the code? Is it "just" for a test bench? Or 
is it for a "real" hardware (FPGA)?

Lothar Miller wrote:
> sreeram sam wrote:
>> can anyone please give me a piece of vhdl code for stuck at faults
>> stuck-at-0 and stuck-at-1 for any sequential and/or combination
>> circuits, just need it to start from the scratch.
> So you want to recognize a stucked/failed signal? Then define a
> stuck-at-1: how long must the signal be '1' to be stucked at '1'?
>
> Or do you want to memorize a fault signal (even when the fault
> disapears) to see later, that there was a fault? Then you need a latch.
>
> What do you want to do with the code? Is it "just" for a test bench? Or
> is it for a "real" hardware (FPGA)?


yes i need to recognize the fault, the code is for simulation only 
purpose only not for any implementation.
the fault may be a permanent one for a particular circuit. i dont want 
to use a latch and complicate code so much.

thanks Miller

Try this as a concurrent statement (without any process):

1

    assert not(now>0 ns and sig='1' and sig'quiet(300 ns)) 

2

        report "sig stuck at '1' for 300ns" severity warning;

3

4

    assert not(now>0 ns and sig='0' and sig'quiet(400 ns))

5

        report "sig stuck at '0' for 400ns" severity warning;

Lothar Miller wrote:
> Try this as a concurrent statement (without any process):
>

1

>     assert not(now>0 ns and sig='1' and sig'quiet(300 ns))

2

>         report "sig stuck at '1' for 300ns" severity warning;

3

> 

4

>     assert not(now>0 ns and sig='0' and sig'quiet(400 ns))

5

>         report "sig stuck at '0' for 400ns" severity warning;

6

>

kindly give me the declaration parts also.(entity port)

thanks

> kindly give me the declaration parts also.(entity port)
Because you want to use this code in a test bench, there is no port in 
the entity.

You can use this code snippet for any signal in any architecture in any 
part of your design. So the only thing missing is:

1

   signal sig : std_logic := '0';

And if your signal is named toggle then the stuck-at-one test will 
read:

1

    assert not(now>0 ns and toggle='1' and toggle'quiet(300 ns)) 

2

        report "toggle stuck at '1' for 300ns" severity warning;

Lothar Miller wrote:
>> kindly give me the declaration parts also.(entity port)
> Because you want to use this code in a test bench, there is no port in
> the entity.
>
> You can use this code snippet for any signal in any architecture in any
> part of your design. So the only thing missing is:
>

1

>    signal sig : std_logic := '0';

2

>

>
> And if your signal is named toggle then the stuck-at-one test will
> read:
>

1

>     assert not(now>0 ns and toggle='1' and toggle'quiet(300 ns))

2

>         report "toggle stuck at '1' for 300ns" severity warning;

3

>

so can i have this snippet at the end of my work space before i end the 
architecture?
will tat way work?

If I were YOU, then I would simply TRY it that way...  :-/

B.Haritha wrote:
> Please help me how to write code for fault occuring in lowerbits of the
> alu.
Pls start a new thread for a new question!

And show what you already have and ask for a particular problem. "To 
help someone" doesn't mean "do all the work and present the final 
solution"...