EmbDev.net

Forum: FPGA, VHDL & Verilog vhdl code for stuck at faults


von sreeram s. (sresam89)


Rate this post
0 useful
not useful
dear all

can anyone please give me a piece of vhdl code for stuck at faults 
stuck-at-0 and stuck-at-1 for any sequential and/or combination 
circuits, just need it to start from the scratch.

I OWE you members..

:
von user (Guest)


Rate this post
0 useful
not useful
stuck at 0 is a AND with a control input, control input = 0 inserts a 
fault
stuck at 1 is a OR  with a control input, control input = 1 inserts a 
fault

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
sreeram sam wrote:
> can anyone please give me a piece of vhdl code for stuck at faults
> stuck-at-0 and stuck-at-1 for any sequential and/or combination
> circuits, just need it to start from the scratch.
So you want to recognize a stucked/failed signal? Then define a 
stuck-at-1: how long must the signal be '1' to be stucked at '1'?

Or do you want to memorize a fault signal (even when the fault 
disapears) to see later, that there was a fault? Then you need a latch.

What do you want to do with the code? Is it "just" for a test bench? Or 
is it for a "real" hardware (FPGA)?

von sreeram s. (sresam89)


Rate this post
0 useful
not useful
Lothar Miller wrote:
> sreeram sam wrote:
>> can anyone please give me a piece of vhdl code for stuck at faults
>> stuck-at-0 and stuck-at-1 for any sequential and/or combination
>> circuits, just need it to start from the scratch.
> So you want to recognize a stucked/failed signal? Then define a
> stuck-at-1: how long must the signal be '1' to be stucked at '1'?
>
> Or do you want to memorize a fault signal (even when the fault
> disapears) to see later, that there was a fault? Then you need a latch.
>
> What do you want to do with the code? Is it "just" for a test bench? Or
> is it for a "real" hardware (FPGA)?


yes i need to recognize the fault, the code is for simulation only 
purpose only not for any implementation.
the fault may be a permanent one for a particular circuit. i dont want 
to use a latch and complicate code so much.

thanks Miller

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
Try this as a concurrent statement (without any process):
    assert not(now>0 ns and sig='1' and sig'quiet(300 ns)) 
        report "sig stuck at '1' for 300ns" severity warning;

    assert not(now>0 ns and sig='0' and sig'quiet(400 ns))
        report "sig stuck at '0' for 400ns" severity warning;

von sreeram s. (sresam89)


Rate this post
0 useful
not useful
Lothar Miller wrote:
> Try this as a concurrent statement (without any process):
>
>     assert not(now>0 ns and sig='1' and sig'quiet(300 ns))
>         report "sig stuck at '1' for 300ns" severity warning;
> 
>     assert not(now>0 ns and sig='0' and sig'quiet(400 ns))
>         report "sig stuck at '0' for 400ns" severity warning;
> 

kindly give me the declaration parts also.(entity port)

thanks

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
> kindly give me the declaration parts also.(entity port)
Because you want to use this code in a test bench, there is no port in 
the entity.

You can use this code snippet for any signal in any architecture in any 
part of your design. So the only thing missing is:
   signal sig : std_logic := '0';

And if your signal is named toggle then the stuck-at-one test will 
read:
    assert not(now>0 ns and toggle='1' and toggle'quiet(300 ns)) 
        report "toggle stuck at '1' for 300ns" severity warning;  

von sreeram s. (sresam89)


Rate this post
0 useful
not useful
Lothar Miller wrote:
>> kindly give me the declaration parts also.(entity port)
> Because you want to use this code in a test bench, there is no port in
> the entity.
>
> You can use this code snippet for any signal in any architecture in any
> part of your design. So the only thing missing is:
>
>    signal sig : std_logic := '0';
> 
>
> And if your signal is named toggle then the stuck-at-one test will
> read:
>
>     assert not(now>0 ns and toggle='1' and toggle'quiet(300 ns))
>         report "toggle stuck at '1' for 300ns" severity warning;
> 

so can i have this snippet at the end of my work space before i end the 
architecture?
will tat way work?

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
If I were YOU, then I would simply TRY it that way...  :-/

von B.Haritha (Guest)


Attached files:

Rate this post
0 useful
not useful
The sender file is an base paper. It is about faults in arithmetic logic 
unit, it is based on hardware partition in time redundancy technique. 
For this we have to write code on faults, that is, we have to check for 
fault occuring in lowerbits of operands. How to check faults in 
lowerbits of operands. This is because our process will be based on the 
condition of narrow width value technique. Please help me how to write 
code for fault occuring in lowerbits of the alu.

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
B.Haritha wrote:
> Please help me how to write code for fault occuring in lowerbits of the
> alu.
Pls start a new thread for a new question!

And show what you already have and ask for a particular problem. "To 
help someone" doesn't mean "do all the work and present the final 
solution"...

von B.Haritha (Guest)


Rate this post
0 useful
not useful
> B.Haritha wrote:
> Please help me how to write code for fault occuring in lowerbits of the
> alu.
>
> Pls start a new thread for a new question!
>
> And show what you already have and ask for a particular problem. "To
> help someone" doesn't mean "do all the work and present the final
> solution"...

     Please,, kindly visit the above paper.. in that we. Have two 
diagrams which will be known as fault detection and fault diagnosis.. 
based on those two diagrams included algorithm only I have to write an 
verilog code for fault detection.. as well as diagnosis. So, kindly help 
me with this.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.