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fOLLOWING are the errors i'm getting now... cic.vhd functional code is proper without errors.... but test bench has some errors.. can you pls help now ? ------------------------------------------------------------------------ ------------------------------------------------------------------ ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 139: Syntax error near "process". ERROR:HDLCompiler:837 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 145: Type void does not match with a string literal ERROR:HDLCompiler:1728 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 146: Type error near line ; current type line; expected type void ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 147: Syntax error near "variable". ERROR:HDLCompiler:620 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 147: Near std_logic_vector ; type conversion does not match type void ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 148: Syntax error near "begin". ERROR:HDLCompiler:62 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 150: output_tmp is not a variable ERROR:HDLCompiler:841 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 152: Expecting type text for <file_out>. ERROR:HDLCompiler:187 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 152: Actual file_out of formal f must be a file ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 145: Syntax error near "file".r "process". ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 154: Syntax error near end if ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- This is what i have to do.... Generate the free running clock, reset for one cycle and ce_r (decimated clock that generates one clock pulse for every 5 clock cycles). Clock enable (ce) can be tied to logic 1 so the filter is always enabled). 3. Testing at 8 MHz passband: In this region, the filter is supposed to pass the sine wave with some change on magnitude. Apply an 8 MHz sine wave sampled by 80 MHz. This means you need 10 samples, each one applied at a 80 MHz clock and it is repeating. Read the input data samples from a file using TEXT IO and apply the input to the design. Read the output values from the waveform and draw both of the waveforms on the same graph. ---------- Post added at 16:56 ---------- Previous post was at 16:51 ---------- ------------------------------------------------------------------------ ------------------------------------------------------------------------ ---------- ------------------------------------------------------------------------ ------------------------------------------------------------------------ ---------- ------------------------------------------------------------------------ ------------------------------------------------------------------------ ---------- ------------------------------------------------------------------------ ------------------------------------------------------------------------ ------------------------------------------------------------------------ ------------------------------------------------------------------------ ------------------------------------------------------------------------ -------------- below are the 10 samples of 8 MHz wave taken at equal sine angles of 36 degrees and normalised...i.e, multiplied by 2^17 (input data width 0:17) and then converted to signed binary number.. 010010110011110010 011110011011110000 011110011011110000 010010110011110010 000000000000000000 101101001100001110 100001100100010000 100001100100010000 101101001100001110 000000000000000000 these inputs should be feed to the cic filter..