-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:32:29 09/26/2011 -- Design Name: -- Module Name: Z:/lab3/CICTEST.vhd -- Project Name: lab3 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: cic -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use std.textio.all; use ieee.std_logic_textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY CICTEST IS END CICTEST; ARCHITECTURE behavior OF CICTEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT cic PORT( clk : IN std_logic; ce : IN std_logic; ce_r : IN std_logic; rst : IN std_logic; d : IN std_logic_vector(17 downto 0); q : OUT std_logic_vector(29 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal ce : std_logic := '0'; signal ce_r : std_logic := '0'; signal rst : std_logic := '0'; signal d : std_logic_vector(17 downto 0) := (others => '0'); --Outputs signal q : std_logic_vector(29 downto 0); file in_file:text is in "cic_in.txt"; variable inline: line; -- Clock period definitions constant clk_period : time := 12.5 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: cic PORT MAP ( clk => clk, ce => ce, ce_r => ce_r, rst => rst, d => d, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- reset process reset: process begin rst <= '1'; wait for clk_period; rst <= '0'; wait for clk_period*10000000; end process; -- clk enable process cenable: process begin ce <= '1'; wait; end process; -- decimated clk process cenable_r: process begin ce_r <= '0'; wait for clk_period*5; ce_r <= '1'; wait for clk_period; end process; -- generating i/p file ip: process (clk) file in_file:text is in "cic_in.txt"; variable inline: line; variable in_tmp: std_logic_vector(17 downto 0); begin if(clk'event and clk='1') then if not endfile(in_file)then readline(in_file,inline); read(inline,in_tmp); d <= in_tmp; end if; end process ip; --------------------- -- generating o/p file op: process (clk) file file_out:text is out "cic_out.txt"; variable line_out : line; variable output_tmp : std_logic_vector(29 downto 0); begin if(clk'event and clk='1') then output_tmp := q; write(line_out, output_tmp); writeline(file_out,line_out); end if; end process op; --------------------- END;