> I shouldn't be using "wait for" and instead turn it syncronous to the
> clock, right?
Thats the only possibility.
> Also I won't be using this on a FPGA,
So just simulating?
> but I do need the simulation to work.
Then your task is fairly easy. You can use the whole language VHDL, not
only those little parts of it which are synthesizable...
> Do you beleive the problem with the state machine is conected to the use
> of these time delaying commands?
No, its something like this:
1 | contador := contador + 1;
|
This "counter" runs in a combinatorial process. And so you created a
combinational loop (aka. combinatorial loop). And that is a counter
running without any clock with theoretically maximum speed. But
practially its just a random noise generator... :-/
And also:
You cannot assign a value to a signal out of two processes. This will
result in a driver conflict and you will get 'X' in your simulation...