library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
   port(count:out std_logic_vector(3 downto 0);
        clk:in std_logic;
        reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is
    
   component ha port (a: in  std_logic;
                      b: in  std_logic;
                      sum: out std_logic;
                      c_out: out std_logic);
   end component;
   
   component fa port (a, b, cin : in std_logic;
                      sum, c_out : out std_logic);
   end component;
   
   signal ain,s,c:std_logic_vector(3 downto 0);
   signal bin:std_logic_vector(3 downto 0):="0001";
               
   --configuration specification   
   for all:ha use entity work.ha(rtl);
   for all:fa use entity work.fa(fa_behav);
      
   begin
      u1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
      u2:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
      u3:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
      u4:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));
      
      
      counter:process(clk, reset) --process(sensitivity list)
      begin
         if reset'event and (reset = '1') then 
            ain <= (others => '0'); 
         
         elsif (clk'event and clk='1') then
            ain <= s; 
            count <= s;
                
         end if;
      end process;
           
end behav_counter4; 

 
       counter:process(clk, reset) --process(sensitivity list)
       begin
          if (reset = '1') then
             ain <= (others => '0');
 
          elsif (clk'event and clk='1') then
             ain <= s;
             count <= s;
             bin <= "0001";
          end if;
       end process;

>           elsif (clk'event and clk='1') then
>              ain <= s;
>              count <= s;
>              bin <= "0001";
>           end if;
>        end process;
>